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mitsubishi microcomputers M37754FFCGP m37754ffchp description the M37754FFCGP and the m37754ffchp are single-chip micro- computers designed with high-performance cmos silicon gate tech- nology, including the internal flash memory. these are housed in 100-pin plastic molded qfp. these microcomputers have a cpu and a bus interface unit. the cpu is a 16-bit parallel processor that can also be switched to per- form 8-bit parallel processing, and the bus interface unit enhances the memory access efficiency to execute instructions fast. in addition to the 7700 family basic instructions, the M37754FFCGP and the m37754ffchp have 6 special instructions which contain in- structions for signed multiplication/division; these added instructions improve the servo arithmetic performance to control hard disk drives and so on. these microcomputers also include the flash memory, ram, mul- tiple-function timers, motor control function, serial i/o, a-d converter, d-a converter, and so on. the internal flash memory can be programed and erased by using a prom programmer or by control of the central processing unit (cpu). therefore, these microcomputers can change the program easily even after they are mounted on the board. distinctive features ? number of basic machine instructions .................................... 109 (103 basic instructions of 7700 family + 6 special instructions) ? memory size flash memory ................................ 120 kbytes ram ................................................3968 bytes ? instruction execution time the fastest instruction at 40 mhz frequency ...................... 100 ns ? single power supply ....................................................... 5v 10 % ? low power dissipation (at 40 mhz frequency) ....... 125 mw (typ.) ? interrupts ........................................................... 21 types, 7 levels ? multiple-function 16-bit timer ................................................... 5+3 (three-phase motor drive waveform or pulse motor control wave- form output) ? serial i/o (uart or clock synchronous) ..................................... 2 ? 10-bit a-d converter ............................................ 8-channel inputs ? 8-bit d-a converter ............................................ 2-channel outputs ? 12-bit watchdog timer ? programmable input/output (ports p0p11) ............................ 87 ? small package [m37754ffchp] ................................. 100-pin fine pitch qfp (lead pitch : 0.5 mm) ? supply voltage ................................................... v cc = 5 v 10 % ? program/erase voltage ...................................... v pp = 12 v 5 % ? programming method ........................ programming in unit of byte ? erasing method ............................................................................. batch erasing and 2-division-block erasing (in cpu reprogramming mode) ? program/erase control by software command ? number of times for programming/erasing .............................. 100 preliminary notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version application control devices for personal computer peripheral equipment such as cd-rom drives, hard disk drives, high density fdd, printers control devices for office equipment such as copiers and facsimiles control devices for industrial equipment such as communication and measuring instruments control devices for equipment required for motor control such as in- verter air conditioner and general purpose inverter
2 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version outline 100p6s-a M37754FFCGP pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p7 0 /an 0 ? p9 5 /int 3 /ki 4 ? p9 4 /cs 4 /rtp1 3 ? p9 0 /cs 0 ? p6 7 /tb2 in ? p6 6 /tb1 in ? p6 5 /tb0 in ? p6 4 /int 2 ? p6 3 /int 1 ? p6 2 /int 0 ? p6 1 /ta4 in ? p6 0 /ta4 out ? p5 7 /ta3 in /ki 3 ? p5 6 /ta3 out /ki 2 ? p5 5 /ta2 in /ki 1 ? p5 4 /ta2 out /ki 0 ? p5 3 /ta1 in /w/rtp0 3 ? p5 2 /ta1 out /u/rtp0 2 ? p5 1 /ta0 in /v/rtp0 1 ? p5 0 /ta0 out /w/rtp0 0 ? p4 7 ? p4 6 ? p4 5 ? p4 4 ? p4 3 ? p4 2 / f 1 ? p4 1 /rdy ? 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 p9 3 /cs 3 /a 22 /rtp1 2 ? p9 2 /cs 2 /a 21 /u/rtp 1 1 ? p9 1 /cs 1 /a 20 /v/rtp1 0 ? ? p4 0 /hold ? byte cnv ss ? reset ? x in ? x out ? e/rd v ss v cc ? p3 3 /hlda ? p3 2 /ale ? p3 1 /bhe ? p3 0 /wr ? p11 7 /d 15 ? p11 6 /d 14 ? p11 5 /d 13 ? p11 4 /d 12 ? p11 3 /d 11 ? p11 0 /d 8 ? p10 7 /d 7 /la 7 ? p10 6 /d 6 /la 6 ? p10 5 /d 5 /la 5 ? p10 4 /d 4 /la 4 ? p10 3 /d 3 /la 3 ? p10 2 /d 2 /la 2 ? p10 1 /d 1 /la 1 ? p10 0 /d 0 /la 0 ? p2 7 /a 23 ? p2 3 /a 19 ? p2 2 /a 18 ? p2 1 /a 17 ? p2 0 /a 16 ? p1 7 /a 15 ? p1 6 /a 14 ? p1 5 /a 13 ? p1 4 /a 12 ? p1 3 /a 11 ? p1 2 /a 10 ? p1 1 /a 9 ? p1 0 /a 8 ? p0 7 /a 7 ? p0 6 /a 6 ? p0 5 /a 5 ? p0 4 /a 4 ? p0 3 /a 3 ? p0 2 /a 2 ? p0 1 /a 1 ? p0 0 /a 0 ? p11 2 /d 10 ? p11 1 /d 9 p8 7 /t x d 1 ? p8 6 /r x d 1 ? p8 5 /clk 1 ? p8 4 /cts 1 /rts 1 /da 1 /int 4 ? p8 3 /t x d 0 ? p8 2 /r x d 0 /clks 0 ? p8 1 /clk 0 ? v cc av cc v ref ? av ss v ss p7 7 /an 7 /ad trg ? p7 6 /an 6 ? p7 5 /an 5 ? p7 4 /an 4 ? p7 3 /an 3 ? p7 2 /an 2 ? p7 1 /an 1 ? p8 0 /cts 0 /rts 0 /clks 1 /da 0 ? M37754FFCGP
3 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memory version m37754ffchp pin configuration (top view) outline 100p6q-a 26 27 ? p4 3 ? p4 2 / f 1 ? p4 1 /rdy ? p4 0 /hold ? byte cnv ss ? reset ? x in ? x out ? e/rd v ss v cc ? p3 3 /hlda ? p3 2 /ale ? p3 1 /bhe ? p3 0 /wr ? p11 7 /d 15 ? p11 6 /d 14 ? p11 5 /d 13 ? p11 4 /d 12 ? p11 3 /d 11 ? p11 2 /d 10 ? p11 1 /d 9 ? p11 0 /d 8 ? p10 7 /d 7 /la 7 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p0 2 /a 2 ? p0 1 /a 1 ? p0 0 /a 0 ? p8 7 /t x d 1 ? p8 6 /r x d 1 ? p8 5 /clk 1 ? p8 4 /cts 1 /rts 1 /da 1 /int 4 ? p8 3 /t x d 0 ? p8 2 /r x d 0 /clks 0 ? p8 1 /clk 0 ? v cc av cc v ref ? av ss v ss p7 7 /an 7 /ad trg ? m37754ffchp p7 6 /an 6 ? p7 5 /an 5 ? p7 4 /an 4 ? p7 3 /an 3 ? p7 2 /an 2 ? p7 1 /an 1 ? p7 0 /an 0 ? p9 5 /int 3 /ki 4 ? p8 0 /cts 0 /rts 0 /clks 1 /da 0 ? 51 52 ? p10 6 /d 6 /la 6 ? p10 5 /d 5 /la 5 ? p10 4 /d 4 /la 4 ? p10 3 /d 3 /la 3 ? p10 2 /d 2 /la 2 ? p10 1 /d 1 /la 1 ? p10 0 /d 0 /la 0 ? p2 7 /a 23 ? p2 3 /a 19 ? p2 2 /a 18 ? p2 1 /a 17 ? p2 0 /a 16 ? p1 7 /a 15 ? p1 6 /a 14 ? p1 5 /a 13 ? p1 4 /a 12 ? p1 3 /a 11 ? p1 2 /a 10 ? p1 1 /a 9 ? p1 0 /a 8 ? p0 7 /a 7 ? p0 6 /a 6 ? p0 5 /a 5 ? p0 4 /a 4 ? p0 3 /a 3 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 p9 4 /cs 4 /rtp1 3 ? p9 3 /cs 3 /a 22 /rtp1 2 ? p9 0 /cs 0 ? p6 7 /tb2 in ? p6 6 /tb1 in ? p6 5 /tb0 in ? p6 4 /int 2 ? p6 1 /ta4 in ? p6 0 /ta4 out ? p5 7 /ta3 in /ki 3 ? p5 6 /ta3 out /ki 2 ? p5 5 /ta2 in /ki 1 ? p5 4 /ta2 out /ki 0 ? p5 3 /ta1 in /w/rtp0 3 ? p5 2 /ta1 out /u/rtp0 2 ? p5 1 /ta0 in /v/rtp0 1 ? p5 0 /ta0 out /w/rtp0 0 ? p4 7 ? p4 6 ? p4 5 ? p4 4 ? p9 2 /cs 2 /a 21 /u/rtp1 1 ? p9 1 /cs 1 /a 20 /v/rtp1 0 ? p6 3 /int 1 ? p6 2 /int 0 ?
4 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version block diagram p2 (5) input/output port p2 p1 (8) input/output port p1 p0 (8) input/output port p0 flash memory 120 kbytes p3 (4) input/output port p3 p8(8) p7(8) p9(6) p6(8) p5(8) p4(8) input/output port p4 p11(8) p10 (8) input/output port p8 input/output port p7 input/output port p9 input/output port p6 input/output port p5 input/output port p11 clock generating circuit instruction register(8) ram 3968 bytes timer ta0(16) timer ta1(16) timer ta2(16) timer ta3(16) timer tb0(16) timer tb1(16) timer tb2(16) watchdogtimer uart 0(9) uart 1(9) a-d converter(10) d-a 0 converter(8) d-a 1 converter(8) timer ta4(16) address bus data bus(even) data buffer db h (8) data buffer db l (8) instruction queue buffer q 0 (8) instruction queue buffer q 1 (8) instruction queue buffer q 2 (8) incrementer(24) program address register pa(24) data address register da(24) processor status register ps(11) direct page register dpr(16) stack pointer s(16) incrementer/decrementer(24) program counter pc(16) program bank register pg(8) data bank register dt(8) index register y(16) index register x(16) accumulator b(16) accumulator a(16) arithmetic logic unit(16) input buffer register ib(16) data bus(odd) x in reset input reset (5v) v cc cnv ss (0v) av ss (5v) av cc reference voltage input (0v) v ss clock output x out v ref clock input e enable output input/output port p10 bus width select input byte
5 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memory version functions (microcomputer mode) functions parameter number of basic machine instructions instruction execution time memory size input/output ports multiple-function timers serial i/o a-d converter d-a converter watchdog timer dead-time timer interrupts clock generating circuit supply voltage power dissipation input/output characteristic memory expansion operating temperature range device structure package 109 (103 basic instructions of 7700 family + 6 special instructions) 100 ns (the fastest instruction at external clock 40 mhz frequency) 120 kbytes 3968 bytes 8-bit 9 5-bit 1 4-bit 1 6-bit 1 16-bit 5 16-bit 3 (uart or clock synchronous serial i/o) 2 10-bit 1(8 channels) 8-bit 2 12-bit 1 8-bit 3 5 external types, 16 internal types (each interrupt can be set to priority levels 0 C 7.) built-in (externally connected to a ceramic resonator or quartz crystal resonator) 5 v10 % 125 mw (at external clock 40 mhz frequency) 5 v 5 ma maximum 16 mbytes C20 to 85 c cmos high-performance silicon gate process 100-pin plastic molded qfp input/output withstand voltage output current flash memory ram p0, p1, p4Cp8, p10, p11 p2 p3 p9 ta0, ta1, ta2, ta3, ta4 tb0, tb1, tb2 functions (flash memory mode) functions parameter supply voltage program/erase voltage flash memory mode programming method erasing method program/erase control method command number number of times for program/erase 5 v 10 % 12 v 5 % 3 modes (parallel i/o, serial i/o, cpu reprogramming) programming in unit of byte/120 kbytes programming in unit of byte/120 kbytes programming in unit of byte/112 kbytes batch erasing/120 kbytes batch erasing/120 kbytes batch erasing/112 kbytes or 2-division-block erasing 2-division-block erasing: 56-kbyte area to be erased is selectable. program/erase control by software command 7 commands 7 commands 7 commands 100 parallel i/o mode serial i/o mode cpu reprogramming mode parallel i/o mode serial i/o mode cpu reprogramming mode parallel i/o mode serial io mode cpu reprogramming mode
6 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version pin description (microcomputer mode) functions input input input output output input input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input/ output name pin v cc , v ss cnv ss _____ reset x in x out __ e byte (note) av cc , av ss v ref p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 3 , p2 7 p3 0 Cp3 3 p4 0 Cp4 7 p5 0 Cp5 7 p6 0 Cp6 7 p7 0 Cp7 7 p8 0 Cp8 7 p9 0 Cp9 5 supply 5 v10 % to v cc and 0 v to v ss . this pin controls the processor mode. connect to v ss for single-chip mode or memory expansion mode. connect to v cc for microprocessor mode. this is reset input pin. the microcomputer is reset when supplying l level to this pin. these are i/o pins of internal clock generating circuit. connect a ceramic or quartz- crystal resonator between x in and x out . when an external clock is used, the clock source should be connected to the x in pin and the x out pin should be left open. __ this pin outputs enable signal e, which indicates access state of data bus for single-chip mode. ___ this pin outputs rd signal for memory expansion mode or microprocessor mode. this pin determines whether the external data bus is 8-bit width or 16-bit width for memory expansion mode or microprocessor mode. the width is 16 bits when l signal inputs and 8 bits when h signal inputs. power supply for the a-d converter and the d-a converter. connect av cc to v cc and av ss to v ss externally. this is reference voltage input pin for the a-d converter and the d-a converter. in single-chip mode, port p0 is an 8-bit i/o port. this port has an i/o direction register and each pin can be programmed for input or output. these ports are in the input mode when reset. address (a 0 - a 7 ) is output in memory expansion mode or microprocessor mode. in single-chip mode, these pins have the same functions as port p0. address (a 8 - a 15 ) is output in memory expansion mode or microprocessor mode. in single-chip mode, these pins have the same functions as port p0. address (a 16 - a 19 , a 23 ) is output in memory expansion mode or microprocessor mode. in single-chip mode, these pins have the same functions as port p0. in memory ___ ____ _____ expansion mode or microprocessor mode, wr, bhe, ale, and hlda signals are output. in single-chip mode, these pins have the same functions as port p0. in memory _____ expansion mode or microprocessor mode, p4 0 , p4 1 , and p4 2 become hold and ____ rdy input pins, and clock f 1 output pin respectively. functions of other pins are the same as in single-chip mode. in memory expansion mode, p4 2 can be programmed as i/o port. in addition to having the same functions as port p0 in single-chip mode, these pins also function as i/o pins for timer a0, timer a1, timer a2, timer a3, output pins for motor drive waveform, and input pins for key input interrupt. in addition to having the same functions as port p0 in single-chip mode, these pins ____ also function as i/o pins for timer a4, input pins for external interrupt input int 0 , ____ ____ int 1 , and int 2 , and input pins for timer b0, timer b1, and timer b2. in addition to having the same functions as port p0 in single-chip mode, these pins also function as input pins for a-d converter. in addition to having the same functions as port p0 in single-chip mode, these pins also function as i/o pins for uart0, uart1, output pins for d-a converter, and ____ input pin for int 4 . in addition to having the same functions as port p0 in single-chip mode, these pins ___ also function as input pin for int 3 , output pins for motor drive waveform. in memory expansion mode and microprocessor mode, these pins can be ___ ___ programmed as address (a 20 - a 22 ) or output pins for cs 0 C cs 4 power supply cnv ss input reset input clock input clock output enable output bus width select input analog supply input reference voltage input i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 i/o port p5 i/o port p6 i/o port p7 i/o port p8 i/o port p9 note: it is impossible to change the input level of the byte pin in each bus cycle. in other words, bus width cannot be switched dyna mically. fix the input level of the byte pin to h or l according to the bus width used.
7 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memory version functions i/o input/ output name pin p10 0 Cp10 7 i/o port p10 in single-chip mode, these pins have the same functions as port p0. in memory expansion mode or microprocessor mode, these pins become data i/o pins and operate as follows: (1) when using 16-bit width as external data bus width: ? accessing external memory pins value is input into low-order internal data bus (db 0 to db 7 ). value of low-order internal data bus (db 0 to db 7 ) is output to these pins. ? accessing internal memory these pins enter high impedance state. value of internal data bus is output to these pins. (2) when using 8-bit width as external data bus width: ? accessing external memory pins value is input into internal data bus. the value is input into low-order internal data bus (db 0 to db 7 ) when accessing an even address; it is input into high-order internal data bus (db 8 to db 15 ) when accessing an odd address. value of internal data bus is output to these pins. the value of low-order internal data bus (db 0 to db 7 ) is output when accessing an even address; the value of high-order internal data bus (db 8 to db 15 ) is output when accessing an odd address. ? accessing internal memory these pins enter high impedance state. value of internal data bus is output to these pins. when the external bus width is 8 bits, the mode where low-order address (la 0 ___ ___ C la 7 ) is output when rd or wr output is h and data (d 0 C d 7 ) is input/output ___ ___ when rd or wr output is l can be selected in specified external memory area access cycle. in single-chip mode, these pins have the same functions as port p0. in memory expansion mode or microprocessor mode, these pins operate as follows: (1) when using 16-bit width as external data bus width ? accessing external memory the value is input into high-order internal data bus (db 8 to db 15 ) when accessing an odd address; these pins enter high impedance state when not accessing an odd address. value of high-order internal data bus (db 8 -db 15 ) is output to these pins. ? accessing internal memory these pins enter high impedance state. value of internal data bus is output to these pins. (2) when using 8-bit width as external data bus width these pins become i/o port p11 0 C p11 7 . p11 0 Cp11 7 i/o port p11 i/o
8 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version pin description (flash memory parallel i/o mode) pin power supply v pp input bus width select input reset input clock input clock output enable output analog supply input reference voltage input address input (a 0 Ca 7 ) address input (a 8 Ca 15 ) input port p2 input port p3 input port p4 control signal input input port p6 input port p7 input port p8 input port p9 data i/o (d 0 Cd 7 ) input port p11 name input input input input output output input input input input input input input input input input input i/o input input /output supply 5 v 10 % to v cc and 0 v to v ss . connect to 5 v 10 % in read-only mode, connect to 12 v 5 % in read/write mode. connect to v ss . connect to v ss . connect a ceramic resonator between x in and x out . keep it open. connect av cc to v cc and av ss to v ss . connect to v ss . port p0 functions as 8-bit address input (a 0 Ca 7 ). port p1 functions as 8-bit address input (a 8 Ca 15 ). connect to v ss . connect to v ss . keep p4 2 open. connect p4 0 , p4 1 , p4 3 Cp4 7 to v ss . ___ __ __ p5 0 , p5 1 and p5 2 function as the we, oe and ce input pins respectively. p5 4 functions as the a 16 input pin. connect p5 3 to v cc . connect p5 5 , p5 6 and p5 7 to v ss . connect to v ss . connect to v ss . connect to v ss . connect to v ss . function as 8-bit datas i/o pins (d 0 Cd 7 ). connect to vss. functions v cc , v ss cnv ss byte _____ reset x in x out _ e av cc , av ss v ref p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 3 , p2 7 p3 0 Cp3 3 p4 0 Cp4 7 p5 0 Cp5 7 p6 0 Cp6 7 p7 0 Cp7 7 p8 0 Cp8 7 p9 0 Cp9 5 p10 0 Cp10 7 p11 0 Cp11 7
9 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memory version pin description (flash memory serial i/o mode) v cc , v ss cnv ss byte _____ reset x in x out _ e av cc , av ss v ref p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 3 , p2 7 p3 0 Cp3 3 p4 0 Cp4 3 , p4 7 p4 4 p4 5 p4 6 p5 0 , p5 2 Cp5 7 p5 1 p6 0 Cp6 7 p7 0 Cp7 7 p8 0 Cp8 7 p9 0 Cp9 5 p10 0 Cp10 7 p11 0 Cp11 7 pin power supply v pp input bus width select input reset input clock input clock output enable output analog supply input reference voltage input input port p0 input port p1 input port p2 input port p3 input port p4 busy output sda i/o sclk input input port p5 control signal input input port p6 input port p7 input port p8 input port p9 input port p10 input port p11 name input input input input output output input input input input input input output i/o input input input input input input input input input input /output functions supply 5 v 10 % to v cc and 0 v to v ss . connect to 12 v 5 %. connect to v ss or v cc . connect to v ss . connect a ceramic resonator between x in and x out . h is output. connect av cc to v cc and av ss to v ss . input an arbitrary level between the range of v ss and v cc . input h or l, or keep them open. input h or l, or keep them open. input h or l, or keep them open. input h or l, or keep them open. input h or l to p4 0 , p4 1 , p4 3 , p4 7 , or keep them open. keep p4 2 open. this pin is for busy signal output. this pin is for serial data i/o. this pin is for serial clock input. input h or l, or keep them open. __ oe input pin input h or l, or keep them open. input h or l, or keep them open. input h or l, or keep them open. input h or l, or keep them open. input h or l, or keep them open. input h or l, or keep them open.
10 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version basic function blocks the M37754FFCGP and the m37754ffchp have the same func- tions as the m37754m8c-xxxgp and the m37754m8c-xxxhp ex- cept for the following. therefore, refer to the section on the m37754m8c-xxxgp and the m37754m8c-xxxhp. (1) flash memory is included instead of rom. (2) the memory size is different. (3) the memory area modification function is different. (4) part of the peripheral devices control registers is different. (flash memory control register, flash command register, and bits 3, 4 of particular function select register 0 are added.) memory the memory map is shown in figure 1. int 4 a-d conversion uart1 transmission uart1 receive uart0 transmission uart0 receive timer b2 timer b1 timer b0 internal ram 3968 bytes internal flash memory 120 kbytes peripheral devices control registers (refer to fig.2.) interrupt vector table reserved area timer a4 timer a3 timer a2 timer a1 timer a0 watchdog timer brkinstruction 0 divide int 3 int 2 int 1 int 0 reset dbc 000000 16 00ffd2 16 00fffe 16 01ffff 16 01efff 16 010fff 16 : the flash memory area (8 kbytes) where it is impossible to erase/modify in the cpu reprogramming mode. (it is possible to erase/modify in the parallel i/o mode or the serial i/o mode.) note: the internal memory area can be changed. (refer to the section on the memory area modification function.) 00efff 16 001000 16 000fff 16 000080 16 00007f 16 000000 16 000000 16 bank 0 16 bank 1 16 fe0000 16 feffff 16 ffffff 16 ff0000 16 00ffff 16 01ffff 16 010000 16 00ffff 16 00007f 16 010000 16 00ffd2 16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bank fe 16 ? ? ? ? ? ? ? bank ff 16 ? ? ? ? ? ? ? ???????????? fig. 1 memory map
11 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memor y version fig. 2 location of peripheral devices and interrupt control registers 000000 000001 000002 000003 000004 000005 000006 000007 000008 000009 00000a port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register port p9 register port p8 direction register port p9 direction register port p11 register port p11 direction register a-d control register 0 a-d control register 1 a-d register 0 a-d register 1 a-d register 2 a-d register 3 a-d register 4 a-d register 5 a-d register 6 a-d register 7 uart0 transmit/receive mode register uart0 baud rate register uart0 transmit buffer register uart0 transmit/receive control register 0 uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 uart1 receive buffer register 00000b 00000c 00000d 00000e 00000f 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001a 00001b 00001c 00001d 00001e 00001f 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002a 00002b 00002c 00002d 00002e 00002f 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003a 00003b 00003c 00003d 00003e 00003f 000040 000041 000042 000043 000044 000045 000046 000047 000048 000049 00004a count start register one-shot start register up-down register timer a0 register timer a1 register timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register timer b2 register timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 processor mode register 1 watchdog timer register watchdog timer frequency select regsiter chip select control register chip select area register comparator function select register comparator result register d-a register 0 d-a register 1 particular function select register 0 particular function select register 1 int 3 interrupt control register a-d interrupt control register uart0 trasmit interrupt control register uart0 receive interrupt control register uart1 trasmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register 00004b 00004c 00004d 00004e 00004f 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005a 00005b 00005c 00005d 00005e 00005f 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006a 00006b 00006c 00006d 00006e 00006f 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007a 00007b 00007c 00007d 00007e 00007f int 0 interrupt control register int 1 interrupt control register int 2 interrupt control register address (hexadecimal notation) address (hexadecimal notation) port p0 register port p1 register port p0 direction register port p1 direction register port p2 register port p3 register port p2 direction register port p3 direction register port p10 register port p10 direction register waveform output mode register dead-time timer pulse output data register 1 pulse output data register 0 timer a write register flash command register flash memory control register int 4 interrupt control register
12 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memor y version fig. 3 microcomputer internal registers status after reset ( 04 16 ) address port p0 direction register 0 0000 00 16 ( 05 16 ) port p1 direction register ( 08 16 ) port p2 direction register 0000 ( 09 16 ) port p3 direction register 0 0 0 000 ( 15 16 ) port p9 direction register 00 16 ( 0c 16 ) port p4 direction register 00 16 ( 0d 16 ) port p5 direction register 00 16 ( 10 16 ) port p6 direction register 00 16 ( 11 16 ) port p7 direction register 00 16 ( 14 16 ) port p8 direction register 00 16 ( 56 16 ) timer a0 mode register 00 16 ( 57 16 ) timer a1 mode register 00 16 ( 58 16 ) timer a2 mode register 00 16 ( 59 16 ) timer a3 mode register 00 16 ( 5a 16 ) timer a4 mode register 00 16 ( 18 16 ) port p10 direction register 00 16 ( 19 16 ) port p11 direction register 00 16 0 00 0 000 ( 1d 16 ) pulse output data register 0 0 000 0 ??? ( 1e 16 ) a-d control register 0 0 000 0 011 ( 1f 16 ) a-d control register 1 1 0 0 000 ( 34 16 ) uart 0 transmit/receive control register 0 1 0 0 000 ( 3c 16 ) uart 1 transmit/receive control register 0 0 000 0 010 ( 35 16 ) uart 0 transmit/receive control register 1 0 000 0 010 ( 3d 16 ) uart 1 transmit/receive control register 1 0 0 000 ( 42 16 ) one-shot start register 000 ( 45 16 ) timer a write register ( 1a 16 ) waveform output mode register 00 16 ( 1c 16 ) pulse output data register 1 00 16 ( 30 16 ) uart 0 transmit/receive mode register 00 16 ( 38 16 ) uart 1 transmit/receive mode register 00 16 0 000 0 000 ( 44 16 ) up-down register ( 40 16 ) count start register 00 16 0 01 0 000 ( 5b 16 ) timer b0 mode register 0 01 0 000 ( 5c 16 ) timer b1 mode register 0 01 0 000 ( 5d 16 ) timer b2 mode register 0 000 0 000 ( 5e 16 ) processor mode register 0 ( 5f 16 ) processor mode register 1 00 16 ( 60 16 ) address watchdog timer 00 0 0 0000 00 0 0 0000 00 fff 16 ( 61 16 ) watchdog timer frequency select register ( 62 16 ) chip select control register 000 ( 63 16 ) chip select area register ( 6d 16 ) particular function select register 1 ( 64 16 ) comparator function select register ( 66 16 ) comparator result register ( 68 16 ) d-a register 0 ( 6a 16 ) d-a register 1 ( 6c 16 ) particular function select register 0 int 2 interrupt control register processor status register ps 00 16 00 16 program bank register pg contents of ffff 16 program counter pc h contents of fffe 16 program counter pc l 0000 16 ( 6e 16 ) int 4 interrupt control register ( 6f 16 ) int 3 interrupt control register 0 00 000 ?000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ( 72 16 ) uart 0 receive interrupt control register ( 73 16 ) uart 1 transmit interrupt control register ( 74 16 ) uart 1 receive interrupt control register ( 77 16 ) timer a2 interrupt control register ( 78 16 ) timer a3 interrupt control register ( 79 16 ) timer a4 interrupt control register ( 7a 16 ) timer b0 interrupt control register 0 0 0 000 ( 7c 16 ) timer b2 interrupt control register 000 ( 7e 16 ) int 1 interrupt control register ( 70 16 ) a-d interrupt control register ( 71 16 ) uart 0 transmit interrupt control register ( 75 16 ) timer a0 interrupt control register ( 76 16 ) timer a1 interrupt control register 0 0 0 000 ( 7d 16 ) int 0 interrupt control register ( 7b 16 ) timer b1 interrupt control register direct page register dpr 00 0 ( 7f 16 ) 0 00 1?? 0 00 ?? 0 00 data bank register dt contents of other registers and ram are not initiallzed and must be in- itiallzed by software. note : bit 0 of chip select control register (address 62 16) becomes 0 when cnvss pin level is l ; that bit becomes 1 when the pin level is h . 00 16 00 16 00 16 00 16 00 16 00 16 ( 67 16 ) flash memory control register 0 0 0 0000
13 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memory version memory area modification function for the M37754FFCGP and the m37754ffchp, the internal memorys size and address area can be changed by setting bits 2, 3, 4 (memory allocation select bits) of the particular function select reg- ister 0 (see figure 5). figure 4 shows the memory map when chang- ing the internal memory area. external memory area external memory area (reserved area) internal ram 3968 bytes sfr (ml 2 , ml 1 , ml 0 ) = (0, 0, 0) flash memory size : 120 kbytes ram size : 3968 bytes internal ram 3968 bytes sfr external memory area internal flash memory 60 kbytes internal ram 3072 bytes sfr sfr (ml 2 , ml 1 , ml 0 ) = (0, 0, 1) flash memory size : 92 kbytes ram size : 3968 bytes (ml 2 , ml 1 , ml 0 ) = (0, 1, 0) flash memory size : 60 kbytes ram size : 3072 bytes (ml 2 , ml 1 , ml 0 ) = (0, 1, 1) flash memory size : 56 kbytes ram size : 3072 bytes 00 0000 16 00 0080 16 00 0fff 16 00 1000 16 01 efff 16 01 ffff 16 ff ffff 16 00 0000 16 00 0080 16 00 0c7f 16 00 1000 16 00 ffff 16 ff ffff 16 00 0000 16 00 0080 16 00 0c7f 16 00 2000 16 00 ffff 16 ff ffff 16 internal flash memory 48 kbytes internal ram 2048 bytes sfr (ml 2 , ml 1 , ml 0 ) = (1, 0, 0) flash memory size : 48 kbytes ram size : 2048 bytes 00 0000 16 00 0080 16 00 087f 16 00 4000 16 00 ffff 16 ff ffff 16 00 0000 16 00 0080 16 00 0fff 16 00 8000 16 01 efff 16 01 ffff 16 ff ffff 16 ml 0 : memory allocation select bit 0 ml 1 : memory allocation select bit 1 ml 2 : memory allocation select bit 2 internal ram 2048 bytes sfr (ml 2 , ml 1 , ml 0 ) = (1, 0, 1) flash memory size : 32 kbytes ram size : 2048 bytes 00 0000 16 00 0080 16 00 087f 16 00 8000 16 00 ffff 16 ff ffff 16 internal flash memory 60 kbytes internal flash memory 56 kbytes internal ram 2048 bytes sfr sfr (ml 2 , ml 1 , ml 0 ) = (1, 1, 0) flash memory size : 60 kbytes ram size : 2048 bytes 00 0000 16 00 0080 16 00 087f 16 00 1000 16 00 ffff 16 ff ffff 16 external memory area internal ram 2048 bytes (ml 2 , ml 1 , ml 0 ) = (1, 1, 1) flash memory size : 56 kbytes ram size : 2048 bytes 00 0000 16 00 0080 16 00 087f 16 00 2000 16 00 ffff 16 ff ffff 16 note: the internal flash memory area becomes the external memory area in the microprocessor mode. internal flash memory 120 kbytes external memory area (reserved area) internal flash memory 92 kbytes internal flash memory 56 kbytes internal ram 3072 bytes external memory area internal flash memory 32 kbytes external memory area external memory area external memory area external memory area external memory area fig. 4 memory allocation (internal memory area modification by memory allocation select bits)
14 preliminar y notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos micr ocomputer flash memor y version 7 6 543 2 1 0 0 particular function select register 0 external clock input select bit (notes 1, 2) 0 : actuated oscillation circuit; connecting resonator 1 : stopped oscillation circuit; inputting externaly genara ted clock standby state select bit 0 (notes 1, 3) ; when wit or stp instruction is executed in memory expansio n or microprocessor mode 0 : pins p0 to p3, p10, and p11 are for external data bus. 1 : pins p0 to p3, p10, and p11 are for port output or port input. standby state select bit 1 (notes 1, 4) ; in execution of wit or stp instruction 0 : h or l output for pins e/rd, wr 1 : h output for pins e/rd, wr memory allocation select bits 2, 1, 0 (note 2) 0 0 0 : rom 120 kbytes, ram 3968 bytes ( rom : 001000 16 to 1effff 16 , ram : 000080 16 to 000fff 16 ) 0 0 1 : rom 92 kbytes, ram 3968 bytes ( rom:008000 16 to 01efff 16 , ram:000080 16 to 000fff 16 ) 0 1 0 : rom 60 kbytes, ram 3072 bytes ( rom : 001000 16 to 00ffff 16 , ram : 000080 16 to 000c7f 16 ) 0 1 1 : rom 56 kbytes, ram 3072 bytes ( rom:002000 16 to 00ffff 16 , ram:000080 16 to 000c7f 16 ) 1 0 0 : rom 48 kbytes, ram 2048 bytes ( rom : 004000 16 to 00ffff 16 , ram : 000080 16 to 00087f 16 ) 1 0 1 : rom 32 kbytes, ram 2048 bytes ( rom:008000 16 to 00ffff 16 , ram:000080 16 to 00087f 16 ) 1 1 0 : rom 60 kbytes, ram 2048 bytes ( rom : 001000 16 to 00ffff 16 , ram : 000080 16 to 00087f 16 ) 1 1 1 : rom 56 kbytes, ram 2048 bytes ( rom:002000 16 to 00ffff 16 , ram:000080 16 to 00087f 16 ) fix to 0 stp return select bit 0 : watchdog timer is used when returning from stop mode 1 : watchdog timer is not used when returning from stop mode ; t he microcomputer returns at once. address 6c 16 notes 1 : after the expansion function select bit (bit 5 of particula r function select register 1; figure 62) is 1, bits 1, 5 and 6 can be rewritten. 2 : to set bits 1 to 4, continuous-twice-write operation must b e performed to address 6c 16 . 3 : when byte = h (8-bit external bus width), p11 becomes an input/output port independent of bit 5?s contents. 4 : when the signal output disable select bit is 1 and bit 5 is 1, the e/rd pin always outputs l independent of bit 6 ?s cont ents in execution of wit or stp instruction. fig. 5 particular function select register 0 bit configurat ion
15 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memory version flash memory mode the M37754FFCGP and the m37754ffchp have the flash memory mode in addition to the normal operation mode (microcomputer mode). the user can use this mode to perform read, program, and erase operations for the internal flash memory. the M37754FFCGP and the m37754ffchp have three modes the user can choose: the parallel input/output and serial input/output mode, where the flash memory is handled by using the external pro- grammer, and the cpu reprogramming mode, where the flash memory is handled by the central processing unit (cpu). the follow- ing explains these modes. flash memory mode 1 (parallel i/o mode) the parallel i/o mode can be selected by connecting wires as shown in figures 6, 7 and supplying power to the v cc and v pp pins. in this mode, the M37754FFCGP and the m37754ffchp operate as an equivalent of mitsubishis cmos flash memory m5m28f101. however, because the M37754FFCGP and the m37754ffchps in- ternal memory has a capacity of 120 kbytes, programming is avail- able for addresses 01000 16 to 1efff 16 , and make sure that the data in addresses 00000 16 to 00fff 16 and addresses 1f000 16 to 1ffff 16 are ff 16 . note also that the M37754FFCGP and the m37754ffchp does not contain a facility to read out a device iden- tification code by applying a high voltage to address input (a9). be careful not to erratically set program conditions when using a gen- eral-purpose prom programmer. table 1 shows the pin assignments when operating in the parallel input/output mode. table 1. pin assignments of M37754FFCGP and m37754ffchp when operating in the parallel input/output mode v cc v pp v ss address input data i/o __ ce ___ oe ___ we M37754FFCGP/chp v cc cnv ss v ss ports p0, p1, p5 4 port p10 p5 2 p5 1 p5 0 m5m28f101 v cc v pp v ss a 0 Ca 16 d 0 Cd 7 __ ce __ oe ___ we functional outline (parallel input/output mode) in the parallel input/output mode, the M37754FFCGP and the m37754ffchp allows the user to choose an operation mode be- tween the read-only mode and the read/write mode (software com- mand control mode) depending on the voltage applied to the v pp pin. when v pp = v pp l, the read-only mode is selected, and the user can choose one of three states (e.g., read, output disable, or standby) de- ___ ___ ___ pending on inputs to the ce, oe, and we pins. when v pp = v pp h, the read/write mode is selected, and the user can choose one of four states (e.g., read, output disable, standby, or write) depending on in- __ __ ___ puts to the ce, oe, and we pins. table 2 shows assignment states of control input and each state. read __ __ the microcomputer enters the read state by driving the ce, and oe ___ pins low and the we pin high; and the contents of memory corre- sponding to the address to be input to address input pins (a 0 Ca 16 ). are output to the data input/output pins (d 0 Cd 7 ). output disable __ the microcomputer enters the output disable state by driving the ce ___ __ pin low and the we and oe pins high; and the data input/output pins enter the floating state. standby __ the microcomputer enters the standby state by driving the ce pin high. the M37754FFCGP and the m37754ffchp are placed in a power-down state consuming only a minimal supply current. at this time, the data input/output pins enter the floating state. write the microcomputer enters the write state by driving the v pp pin high ___ __ (v pp = v pp h) and then the we pin low when the ce pin is low and __ the oe pin is high. in this state, software commands can be input from the data input/output pins, and the user can choose program or erase operation depending on the contents of this software com- mand. pin mode read output disable standby read output disable standby write read-only read/write __ ce v il v il v ih v il v il v ih v il v il v ih v il v ih v ih table 2. assignment sates of control input and each state __ oe ___ we v ih v ih v ih v ih v il v pp l v pp l v pp l v pp h v pp h v pp h v pp h v pp output floating floating output floating floating input data i/o note: can be v il or v ih . state
16 preliminar y notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos micr ocomputer flash memor y version fig. 6 pin connection of M37754FFCGP when operating in para llel input/output mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p7 0 p9 5 p9 4 p9 0 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 p9 3 p9 2 p9 1 p4 0 byte cnv ss reset x in x out e v ss v cc p3 3 p3 2 p3 1 p3 0 p11 7 p11 6 p11 5 p11 4 p11 3 p11 0 p10 7 p10 6 p10 5 p10 4 p10 3 p10 2 p10 1 p10 0 p2 7 p2 3 p2 2 p2 1 p2 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p0 1 p0 0 a 0 p11 2 p11 1 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 v cc av cc v ref av ss v ss p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p8 0 M37754FFCGP a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 d 0 oe we ce d 1 d 2 d 3 d 4 d 5 d 6 d 7 v ss ] ] a 16 v pp v cc outline 100p6s-a : connect to the ceramic oscillation circuit. indicates the flash memory pin.
17 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memor y version fig. 7 pin connection of m37754ffchp when operating in paral lel input/output mode v cc 26 27 p4 3 p4 2 p4 1 p4 0 byte cnv ss reset x in x out e v ss v cc p3 3 p3 2 p3 1 p3 0 p11 7 p11 6 p11 5 p11 4 p11 3 p11 2 p11 1 p11 0 p10 7 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p0 2 p0 1 p0 0 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 v cc av cc v ref av ss v ss p7 7 m37754ffchp p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 p9 5 p8 0 51 52 p10 6 p10 5 p10 4 p10 3 p10 2 p10 1 p10 0 p2 7 p2 3 p2 2 p2 1 p2 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 p0 7 p0 6 p0 5 p0 4 p0 3 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 p9 4 p9 3 p9 0 p6 7 p6 6 p6 5 p6 4 p6 1 p6 0 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 p4 7 p4 6 p4 5 p4 4 p9 2 p9 1 p6 3 p6 2 v pp d 7 v ss d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 oe we ce a 16 ] ] outline 100p6q-a : connect to the ceramic oscillation circuit. indicates the flash memory pin.
18 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version read-only mode the microcomputer enters the read-only mode by applying v pp l to the v pp pin. in this mode, the user can input the address of a memory location to be read and the control signals at the timing shown in figure 8, and the M37754FFCGP and the m37754ffchp will output the contents of the users specified address from data i/o pin to the external. in this mode, the user cannot perform any opera- tion other than read. fig. 8 read timing read/write mode the microcomputer enters the read/write mode by applying v pp h to the v pp pin. in this mode, the user must first input a software com- mand to choose the operation (e. g., read, program, or erase) to be performed on the flash memory (this is called the first cycle), and then input the information necessary for execution of the command (e.g, address and data) and control signals (this is called the second cycle). when this is done, the M37754FFCGP and the m37754ffchp execute the specified operation. table 3 shows the software commands and the input/output informa- tion in the first and the second cycles. the input address is latched ___ internally at the falling edge of the we input; software commands and other input data are latched internally at the rising edge of the ___ we input. the following explains each software command. refer to figures 9 to 11 for details about the signal input/output timings. table 3. software command (parallel input/output mode) symbol read program program verify erase erase verify reset device identification address input verify address first cycle data input 00 16 40 16 c0 16 20 16 a0 16 ff 16 90 16 address input read address program address adi second cycle data i/o read data (output) program data (input) verify data (output) 20 16 (input) verify data (output) ff 16 (input) ddi (output) note: adi = device identification address : manufacturers code 00000 16 , device code 00001 16 ddi = device identification data : manufacturers code 1c 16 , device code d0 16 x can be v il or v ih . address valid address t rc t a(ce) t wrr t df t a(oe) t dh t olz floating floating t clz t a(ad) v ih v il v ih v il v ih v il v ih v il v oh v ol ce oe we data dout
19 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memory version read command the microcomputer enters the read mode by inputting command code 00 16 in the first cycle. the command code is latched into the ___ internal command latch at the rising edge of the we input. when the address of a memory location to be read is input in the second cycle, with control signals input at the timing shown in figure 9, the M37754FFCGP and the m37754ffchp output the contents of the specified address from the data i/o pins to the external. the read mode is retained until any other command is latched into the command latch. consequently, once the M37754FFCGP and the m37754ffchp enter the read mode, the user can read out the suc- cessive memory contents simply by changing the input address and executing the second cycle only. any command other than the read command must be input beginning from its command code over again each time the user execute it. the contents of the command latch immediately after power-on is 00 16 . fig. 9 timings during reading address valid address t wc t ch t cs t rc t a(ce) t df t wrr t wp t rrw t a(oe) t dh t dh t vsc t clz t olz t ds t a(ad) v ih v il v ih v il v ih v il v ih v il v ih v il v pp h v pp l ce oe we data v pp dout 00 16
20 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version program command the microcomputer enters the program mode by inputting command code 40 16 in the first cycle. the command code is latched into the ___ internal command latch at the rising edge of the we input. when the address which indicates a program location and data are input in the second cycle, the M37754FFCGP and the m37754ffchp internally ___ latch the address at the falling edge of the we input and the data at ___ the rising edge of the we input. the M37754FFCGP and the ___ m37754ffchp start programming at the rising edge of the we in- put in the second cycle and finishes programming within 10 m s as measured by its internal timer. programming is performed in units of bytes. note: a programming operation is not completed by executing the program command once. always be sure to execute a pro- gram verify command after executing the program command. when the failure is found in this verification, the user must re- peatedly execute the program command until the pass. refer to figure 12 for the programming flowchart. program verify command the microcomputer enters the program verify mode by inputting command code c0 16 in the first cycle. this command is used to verify the programmed data after executing the program command. the command code is latched into the internal command latch at the ___ rising edge of the we input. when control signals are input in the second cycle at the timing shown in figure 10, the M37754FFCGP and the m37754ffchp output the programmed addresss contents to the external. since the address is internally latched when the pro- gram command is executed, there is no need to input it in the sec- ond cycle. fig. 10 input/output timings during programming (verify data is output at the same timing as for read.) address program program verify program address t wc t cs t rrw t wp t wph t wp t dp t ds 40 16 d in c0 16 dout t ds t dh t dh verify data output t dh t vsc t ds t wp t wrr t cs t cs t ch t ch t ch t as t ah v ih v il v ih v il v ih v il v ih v il v ih v il v pp h v pp l ce oe we data v pp
21 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memory version erase command the erase command is executed by inputting command code 20 16 in the first cycle and command code 20 16 again in the second cycle. the command code is latched into the internal command latch at the ___ rising edges of the we input in the first cycle and in the second cycle, respectively. the erase operation is initiated at the rising edge of the ___ we input in the second cycle, and the memory contents are collec- tively erased within 9.5 ms as measured by the internal timer. note that data 00 16 must be written to all memory locations before execut- ing the erase command. note: an erase operation is not completed by executing the erase command once. always be sure to execute an erase verify command after executing the erase command. when the fail- ure is found in this verification, the user must repeatedly ex- ecute the erase command until the pass. refer to figure 12 for the erase flowchart. fig. 11 input/output timings during erasing (verify data is output at the same timing as for read.) erase verify command the user must verify the contents of all addresses after completing the erase command. the microcomputer enters the erase verify mode by inputting the verify address and command code a0 16 in the first cycle. the address is internally latched at the falling edge of the ___ we input, and the command code is internally latched at the rising ___ edge of the we input. when control signals are input in the second cycle at the timing shown in figure 11, the M37754FFCGP and the m37754ffchp output the contents of the specified address to the external. note: if any memory location where the contents have not been erased is found in the erase verify operation, execute the op- eration of erase ? erase verify over again. in this case, however, the user does not need to write data 00 16 to memory locations before erasing. address erase erase verify verify address t wc t cs t rrw t wp t wph t wp t de t ds 20 16 20 16 a0 16 dout t ds t dh t dh verify data output t dh t vsc t ds t wp t wrr t cs t cs t ch t ch t ch t as t ah v ih v il v ih v il v ih v il v ih v il v ih v il v pp h v pp l ce oe we data v pp
22 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version reset command the reset command provides a means of stopping execution of the erase or program command safely. if the user inputs command code ff 16 in the second cycle after inputting the erase or program com- mand in the first cycle and again input command code ff 16 in the third cycle, the erase or program command is disabled (i.e., reset), and the M37754FFCGP and the m37754ffchp are placed in the read mode. if the reset command is executed, the contents of the memory does not change. device identification code command by inputting command code 90 16 in the first cycle, the user can read out the device identification code. the command code is latched into ___ the internal command latch at the rising edge of the we input. at this time, the user can read out manufactures code 1c 16 (i.e., mitsubishi) by inputting 0000 16 to the address input pins in the second cycle; the user can read out device code d0 16 (i. e., 1m-bit flash memory) by inputting 0001 16 . these command and data codes are input/output at the same timing as for read.
23 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memory version fig. 12 programming/erasing algorithm flow chart start v cc = 5 v, v pp = v pp h adrs = first location x = 0 write program command write program data duration = 10 m s x = x + 1 write program-verify command 40 16 d in c0 16 00 16 duration = 6 m s x = 25 ? last adrs ? no inc adrs write read command v pp = v pp l device passed device failed verify byte ? verify byte ? fail fail program erase yes yes no pass pass start v cc = 5 v, v pp = v pp h adrs = first location x = 0 write erase command program all bytes = 00 16 all bytes = 00 16 ? write erase command duration = 9.5 ms x = x + 1 write erase-verify command 20 16 20 16 a0 16 00 16 duration = 6 m s x = 1000 ? last adrs ? no inc adrs write read command v pp = v pp l device passed device failed verify byte ? verify byte ? fail fail yes yes no pass pass yes no
24 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version dc electrical characteristics (t a = 25 c, v cc = 5 v 10 %, unless otherwise noted) symbol max. 1 100 30 30 30 10 100 100 30 30 v cc + 1.0 12.6 __ v cc = 5.5 v, ce = v ih v cc = 5.5 v, __ ce = v cc 0.2 v __ v cc = 5.5 v, ce = v il , t rc = 150 ns, i out = 0 ma v pp = v pp h v pp = v pp h 0 v pp v cc v cc 25 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memor y version flash memory mode 2 (serial i/o mode) the M37754FFCGP and the m37754ffchp have a function to seri- ally input/output the software commands, addresses, and data re- quired for operation on the internal flash memory (e. g., re ad, progr am, and er ase) using only a fe w pins . this is called the serial i/ o (input/output) mode . this mode can be selected b y dr iving the __ sda (serial data input/output), sclk (serial clock input ), and oe pins high after connecting wires as shown in figures 13, 14 and powering on the v cc pin and then applying v pp h to the v pp pin. in the serial i/o mode, the user can use seven types of soft ware commands: bank (0, 1) select, read, prog r am, prog r am v er ify , auto erase, and error check. serial input/output is accomplished synchronously with the c lock, beginning from the lsb (lsb first). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p7 0 p9 5 p9 4 p9 0 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 p9 3 p9 2 p9 1 p4 0 byte ]] cnv ss reset x in x out e v ss v cc p3 3 p3 2 p3 1 p3 0 p11 7 p11 6 p11 5 p11 4 p11 3 p11 0 p10 7 p10 6 p10 5 p10 4 p10 3 p10 2 p10 1 p10 0 p2 7 p2 3 p2 2 p2 1 p2 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 p0 7 p0 6 p0 5 p0 4 p0 3 p0 2 p0 1 p0 0 p11 2 p11 1 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 v cc av cc v ref av ss v ss p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p8 0 M37754FFCGP oe v ss v pp v cc sclk sda busy ] ] ]] outline 100p6s-a fig. 13 pin connection of M37754FFCGP when operating in seri al i/o mode : connect the byte pin to vcc or vss. indicates the flash memory pin. : connect to the ceramic oscillation circuit.
26 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version 26 27 p4 3 p4 2 p4 1 p4 0 byte \\ cnv ss reset x in x out e v ss v cc p3 3 p3 2 p3 1 p3 0 p11 7 p11 6 p11 5 p11 4 p11 3 p11 2 p11 1 p11 0 p10 7 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p0 2 p0 1 p0 0 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 v cc av cc v ref av ss v ss p7 7 m37754ffchp p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 p9 5 p8 0 51 52 p10 6 p10 5 p10 4 p10 3 p10 2 p10 1 p10 0 p2 7 p2 3 p2 2 p2 1 p2 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 p0 7 p0 6 p0 5 p0 4 p0 3 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 p9 4 p9 3 p9 0 p6 7 p6 6 p6 5 p6 4 p6 1 p6 0 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 p4 7 p4 6 p4 5 p4 4 p9 2 p9 1 p6 3 p6 2 v pp v ss v cc busy sda sclk \ oe ] : connect to the ceramic oscillation circuit. ]] : connect the byte pin to v cc or v ss . indicates the flash memory pin. outline 100p6q-a fig. 14 pin connection of m37754ffchp when operating in serial i/o mode
27 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memory version functional outline (serial i/o mode) in the serial i/o mode, data is transferred synchronously with the clock using serial input/output. the input data is read from the sda pin into the internal circuit synchronously with the rising edge of the serial clock pulse; the output data is output from the sda pin syn- chronously with the falling edge of the serial clock pulse. data is transferred in units of eight bits. in the first transfer, the user inputs the command code. this is fol- lowed by address input and data input/output according to the con- tents of the command. table 4 shows the software commands used in the serial i/o mode. the following explains each software com- mand. table 4. software command (serial i/o mode) bank 0 select bank 1 select read program program verify auto erase error check number of transfers command first command code input e0 16 e1 16 00 16 40 16 c0 16 30 16 80 16 read address l (input) program address l (input) verify data (output) 30 16 (input) error code (output) second read address h (input) program address h (input) third fourth read data (output) program data (input) bank select command this is the command which specifies the bank of the flash memory, which is to be read/programmed, before executing the read com- mand or the program command (and the program verify command). there are the bank 0 select command (command code e0 16 ), which selects bank 0 (addresses 00000 16 to 0ffff 16 ), and the bank 1 select command (command code e1 16 ), which selects bank 1 (addresses 10000 16 to 1ffff 16 ). when any bank select command is input once, specified bank is valid until the next bank select command is input. accordingly, when the read command or the program command (and the program verify command) is executed to plural bytes in the same bank, if any bank select command is input first, it is unnecessary to input the bank se- lect command again for the following bytes. when selecting the se- rial i/o mode (before bank command input), bank 0 is selected. note: bank select command does not affect the auto erase com- mand, that is to say, when executing the auto erase com- mand, all flash memory is erased collectively regardless of specified bank. and in the same way, the bank select command does not af- fect the error check command. sclk sclk busy oe sda t ch t ch command code input (e0 16 ) 00000111 ? ? sda command code input (e1 16 ) 10000111 busy oe ? ? bank 0 select command bank 1 select command fig. 15 timings during bank select
28 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version read command input command code 00 16 in the first transfer. proceed and input the low-order 8 bits and the high-order 8 bits of the address and pull the __ oe pin low. when this is done, the M37754FFCGP and the m37754ffchp read out the contents of the specified address, and __ then latch it into the internal data latch. when the oe pin is released back high and serial clock is input to the sclk pin, the read data that has been latched into the data latch is serially output from the sda pin. fig. 16 timings during reading ? sclk busy oe sda t ch a 0 a 7 a 8 a 15 d 0 d 7 t ch t cr command code input (00 16 ) read address input (l) read address input (h) read data output t wr read t rc note : when outputting the read data, the sda pin is switched for output at the first falling edge of sclk. the sda pin is placed in the floating state during the period of th (c-e) after the last rising edge of sclk (at the 8th bit). 00000000
29 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memory version program command input command code 40 16 in the first transfer. proceed and input the low-order 8 bits and the high-order 8 bits of the address and then program data. programming is initiated at the last rising edge of the serial clock during program data transfer. the busy pin is driven high during program operation. programming is completed within 10 m s as measured by the built-in timer, and the busy pin is pulled low. note : a programming operation is not completed by executing the program command once. always be sure to execute a pro- gram verify command after executing the program command. in the case of failure in the verification, the user must repeat- edly execute the program command until the pass in the veri- fication. refer to figure 12 for the programming flowchart. program verify command input command code c0 16 in the first transfer. proceed and drive the __ oe pin low. when this is done, the M37754FFCGP and the m37754ffchp verify-read the programmed addresss contents, __ and then latch it into the internal data latch. when the oe pin is re- leased back high and serial clock is input to the sclk pin, the verify data that has been latched into the data latch is serially output from the sda pin. fig. 18 timings during program verify fig. 17 timings during programming sclk busy oe sda t ch a 0 00000010 a 7 a 8 a 15 d 0 d 7 t ch t ch t pc command code input (40 16 ) program address input (l) program address input (h) program data input t wp program sclk busy oe sda d 0 d 7 t crpv command code input (c0 16 ) verify data output t wr verify read t rc note: when outputting the verify data, the sda pin is switched for output at the first falling edge of sclk. the sda pin is placed in the floating state during the period of th (c-e) after the last rising edge of sclk (at the 8th bit). 00000011 ?
30 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version auto erase command input command code 30 16 in the first transfer and command code 30 16 again in the second transfer. when this is done, the M37754FFCGP and the m37754ffchp execute an auto erase command. auto erase is initiated at the last rising edge of the serial clock. the busy pin is driven high during the auto erase operation. auto erase is completed when all memory contents are erased, and the busy pin is pulled low. note: in the auto erase operation, the M37754FFCGP and the m37754ffchp automatically repeat the erase and verify op- erations internally. therefore, erase is completed by execut- ing the command once. error check command input command code 80 16 in the first transfer, and the M37754FFCGP and the m37754ffchp output error information from the sda pin, beginning at the next falling edge of the serial clock. if the e0 of the 8-bit error information is 1, it indicates that a command error has occurred. a command error means that some in- valid commands other than commands shown in table 4 has been input. when a command error occurs, the serial communication circuit sets the corresponding flag and stops functioning to avoid an erroneous programming or erase. when being placed in this state, the serial communication circuit does not accept the subsequent serial clock and data (even including an error check command). therefore, if the user wants to execute an error check command, temporarily drop the v pp pin input to the v pp l level to terminate the serial input/out- put mode. then, place the M37754FFCGP and the m37754ffchp into the serial i/o mode back again. the serial communication circuit is reset by this operation and is ready to accept commands. the er- ror flag alone is not cleared by this operation, so the user can exam- ine the serial communication circuits error conditions before reset. this examination is done by the first execution of an error check command after the reset. the error flag is cleared when the user has executed the error check command. because the error flag is unde- fined immediately after power-on, always be sure to execute the er- ror check command. fig. 20 timings at error checking fig. 19 timings at auto-erasing sclk busy oe sda t ch t ec 00001100 00001100 command code input (30 16 ) command code input (30 16 ) auto-erase ? sclk busy oe sda e0 t ch command code input (80 16 ) error flag output 00000001 ?????? note: when outputting the error flag, the sda pin is switched for output at the first falling edge of the serial clock. the sda pin i s placed in the floating state during the period of th (c-e) after the last rising edge of the serial clock (at the 8th bit). ? ? ?
31 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memory version dc electrical characteristics (ta = 25 c, v cc = 5 v 10 %, v pp = 12 v 5 %, unless otherwise noted) i cc , i pp -relevant standards during read, program, and erase are the same as in the parallel input/output mode. v ih , v il , v oh , v ol , i ih , and i il for __ the sclk, sda, busy, oe pins conform to the microcomputer modes. ac electrical characteristics (t a = 25 c, v cc = 5 v 10 %, v pp = 12 v 5 %, f(x in ) = 40 mhz, unless otherwise noted) symbol max. 10 90 200 (note 4) t ch t cr t wr t rc t crpv t wp t pc t ec t c(ck) t w(ckh) t w(ckl) t r(ck) t f(ck) t d(c-q) t h(c-q) t h(c-e) t su(d-c) t h(c-d) serial transmission interval read waiting time after transmission read pulse width transfer waiting time after read waiting time before program verify programming time transfer waiting time after programming transfer waiting time after erase sclk input cycle time sclk high-level pulse width sclk low-level pulse width sclk rise time sclk fall time sda output delay time sda output hold time sda output hold time (only the 8th bit) sda input set up time sda input hold time parameter ns ns ns ns m s m s ns ns ns ns ns ns ns ns ns ns ns ns unit min. 400 (note 1) 400 (note 1) 320 (note 2) 400 (note 1) 6 400 (note 1) 400 (note 1) 250 100 100 20 20 0 0 120 (note 3) 30 90 limits notes 1: when f(x in ) = 25 mhz or less, calculate the minimum value according to formula 1. formula 1 : 10 9 2: when f(x in ) = 25 mhz or less, calculate the minimum value according to formula 2. formula 2 : 10 9 3: when f(x in ) = 25 mhz or less, calculate the minimum value according to formula 3. formula 3 : 10 9 4: when f(x in ) = 25 mhz or less, calculate the minimum value according to formula 4 formula 4 : 10 9 1 10 f(x in ) 1 8 f(x in ) 1 5 f(x in ) 1 3 f(x in ) ac waveforms sclk sda input test conditions for ac characteristics ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v ?input timing voltage : v il = 0.2 v cc , v ih = 0.8 v cc sda output t c(ck) t r(ck) t d(c-q) t su(d-c) t h(c-d) t h(c-e) t h(c-q) t f(ck) t w(ckl) t w(ckh)
32 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version flash memory mode-3 (cpu reprogramming mode) the M37754FFCGP and the m37754ffchp have the cpu repro- gramming mode where a built-in flash memory is handled by the cen- tral processing unit (cpu). 112 kbytes (addresses 001000 16 to 00efff 16 and addresses 011000 16 to 01efff 16 ) of the 120-kbyte flash memory shown in figure 1 can be reprogrammed (erase and program). remaining 8 kbytes of the flash memory (addresses 00f000 16 to 010fff 16 ) cannot be reprogrammed, but can be read. (it is possible to reprogram this remaining 8 kbytes in the parallel i/o mode and the serial i/o mode). this area of 8 kbytes can be used as an area where the control program of cpu reprogramming mode is stored. in cpu reprogramming mode, the flash memory is handled by writ- ing and reading to/from the flash memory control register (see fig- ure 21) and the flash command register (see figure 22). the cnv ss pin is used as the v pp power supply pin in cpu repro- gramming mode. it is necessary to apply the power-supply voltage of v pp h from the external to this pin. functional outline (parallel input/output mode) figure 21 shows the flash memory control register bit configuration. figure 22 shows the flash command register bit configuration. bit 0 of the flash memory control register is the cpu reprogramming mode select bit. when this bit is set to 1 and v pp h is applied to the cnvss/v pp pin, the cpu reprogramming mode is selected. whether the cpu reprogramming mode is realized or not is judged by reading the cpu reprogramming mode monitor flag (bit 3 of the flash memory control register). bit 1 is a busy flag which becomes 1" during auto erase, erase, and program execution. whether these operations have been completed or not is judged by checking this flag after each command of auto erase, erase, and the program is executed. bits 4, 5 of the flash memory control register are the erase/program area select bits. these bits specify an area where auto erase, erase, and program is operated. when the auto erase and the erase com- mands are executed after an area is specified by these bits, only the specified area is erased. only for the specified area, programming is enabled; for the other areas, programming is disabled. figure 23 shows the processor mode register 0 bit configuration in the cpu reprogramming mode. set bit 1 to 0 (single-chip or memory expansion mode) in the cpu reprogramming mode. set bit 2 (internal memory access bus cycle select bit) to 0. be sure to set data length select flag m to 1" (8-bit length) before- hand because writing and reading of data are operated in unit of byte. fig. 21 flash memory control register bit configuration 76543210 0 0 flash memory control regsiter cpu reprogramming mode select bit (notes 1, 2) 0 : cpu reprogramming mdoe is invalid. (normal operation mode) 1 : when applying 0 v or v pp l to cnv ss /v pp pin, cpu reprogramming mode is invalid. when applying v pp h to cnv ss /v pp pin, cpu reprogramming mode is valid. auto erase/erase/program busy flag 0 : auto erase, erase, and program are completed or not have been executed. 1 : auto erase/erase/program is being executed. cpu reprogramming mode monitor flag 0 : cpu reprogramming mode is invalid. 1 : cpu reprogramming mode is valid. erase/program area select bits 0 5 : addresses 001000 16 to 00efff 16 and addresses 011000 16 to 01efff 16 (total 112 kbytes) 1 0 : addresses 001000 16 to 00efff 16 (total 56 kbytes) 1 1 : addresses 011000 16 to 01efff 16 (total 56 kbytes) fix this bit to ?. fix this bit to ?. notes 1: bit 0 can be reprogrammed only when 0 v is applied to the cnv ss /v pp pin. 2: when bit 0 is ?,?the processor mode does not change even if v pp h is applied to the cnv ss /v pp pin. address 67 16
33 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memory version cpu reprogramming mode operation proce- dure the operation procedure in cpu reprogramming mode is described below. < beginning procedure > ? apply 0 v to the cnvss/v pp pin for reset release. ? set the processor mode register 0 (see figure 23). ? after cpu reprogramming mode control program is transferred to internal ram, jump to this control program on ram. (the follow- ing operations are controlled by this control program). set 1" (8-bit length) to data length select flag m. ? set 1" to the cpu reprogramming mode select bit. apply v pp h to the cnv ss /v pp pin. ? read the cpu reprogramming mode monitor flag to confirm whether the cpu reprogramming mode is valid. ? the operation of the flash memory is executed by software-com- mand-writing to the flash command register . note: the following are necessary other than this: ?control for data which is input from the external (serial i/o etc.) and to be programmed to the flash memory ?initial setting for ports etc. ?writing to the watchdog timer < release procedure > ? apply 0v to the cnv ss /v pp pin. ? set the cpu reprogramming mode select bit to 0. each software command is explained as follows. read command when 00 16 " is written to the flash command register, the M37754FFCGP and the m37754ffchp enter the read mode. the contents of the corresponding address can be read by reading the flash memory (for instance, with the lda instruction etc.) under this condition. the read mode is maintained until another command code is written to the flash command register. accordingly, after setting the read mode once, the contents of the flash memory can continuously be read. after reset and after the reset command is executed, the read mode is set. fig. 22 flash command register bit configuration writing of software command ?0 16 ?0 16 ?0 16 ?0 16 ?+ ?0 16 ?0 16 ?0 16 ?+ ?0 16 ?f 16 ?+ ?f 16 ?read command ?program command ?program verify command ?erase command ?erase verify command ?auto erase command ?reset command note: the flash command register is write-only register. flash command register address 65 16 76 5 4 3 2 1 0 76 5 4 3 2 1 0 00 0 processor mode register 0 internal memory access bus cycle select bit software reset bit interrupt priority detection time select bits clock f 1 output select bit test mode bit processor mode bits 0 0 : single-chip mode 0 1 : memory expansion mode 1 5 : do not select. fix this bit to ?. fix this bit to ?. note: for the description of processor mode register 0, refer to figure 14 on the m37754m8c-xxxgp data sheet. address 5e 16 fig. 23 processor mode register 0 bit configuration in cpu rewrit- ing mode
34 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version program command when 40 16 " is written to the flash command register, the M37754FFCGP and the m37754ffchp enter the program mode. subsequently to this, if the instruction (for instance, sta or ldm in- struction) for writing byte data in the address to be programmed is executed, the control circuit of the flash memory executes the pro- gram. the auto erase/erase/program busy flag of the flash memory control register is set to 1" when the program starts, and becomes 0" when the program is completed. accordingly, after the write in- struction is executed, cpu can recognize the completion of the pro- gram by polling this bit. the programmed area must be specified beforehand by the erase/ program area select bits. during programming, watchdog timer stops with fff 16 set. note: a programming operation is not completed by executing the program command once. always be sure to execute a pro- gram verify command after executing the program command. when the failure is found in this verification, the user must re- peatedly execute the program command until the pass. refer to figure 24 for the flow chart of the programming. program verify command when c0 16 " is written to the flash command register, the M37754FFCGP and the m37754ffchp enter the program verify mode. subsequently to this, if the instruction (for instance, lda in- struction) for reading byte data from the address to be verified (i.e., previously programmed address), the contents which has been writ- ten to the address actually is read. cpu compares this read data with data which has been written by the previous program command. in consequence of the comparison, if not agreeing, the operation of program ? program verify must be executed again. erase command when writing 20 16 twice continuously to the flash command regis- ter, the flash memory control circuit performs erase to the area speci- fied beforehand by the erase/program area select bits. auto erase/erase/program busy flag of the flash memory control reg- ister becomes 1" when erase begins, and it becomes 0" when erase completes. accordingly, cpu can recognize the completion of erase by polling this bit. data 00 16 must be written to all areas to be erased by the program and the program verify commands before the erase command is ex- ecuted. during programming, watchdog timer stops with fff 16 set. note: the erasing operation is not completed by executing the erase command once. always be sure to execute an erase verify command after executing the erase command. when the fail- ure is found in this verification, the user must repeatedly ex- ecute the erase command until the pass. refer to figure 24 for the erasing flowchart. erase verify command when a0 16 " is written to the flash command register, the M37754FFCGP and the m37754ffchp enter the erase verify mode. subsequently to this, if the instruction (for instance, lda in- struction) for reading byte data from the address to be verified, the contents of the address is read. cpu must erase and verify to all erased areas in a unit of address. if the address of which data is not ff 16 " (i.e., data is not erased) is found, it is necessary to discontinue erasure verification there, and execute the operation of erase ? erase verify again. note: by executing the operation of erase ? erase verify again when the memory not erased is found. it is unnecessary to write data 00 16 before erasing in this case.
35 mitsubishi microcomputers M37754FFCGP m37754ffchp preliminary notice: this is not a final specification. some parametric limits are subject to change. shingle-chip 16-bit cmos microcomputer flash memory version fig. 24 flowchart when program/erase/auto erase is executed (1) erase program busy flag = 0 start adrs = first location x = 0 write program command write program data nop 5 10 x = x + 1 write program-verify command 40 16 din c0 16 00 16 duration = 6 m s x = 25 ? last adrs ? no inc adrs write read command device passed device failed verify byte ? verify byte ? fail fail program erase yes yes no pass pass start adrs = first location x = 0 write erase command program all bytes = 00 16 all bytes = 00 16 ? write erase command x = x + 1 write erase-verify command 20 16 20 16 a0 16 00 16 duration = 6 m s x = 1000 ? last adrs ? no inc adrs write read command device passed device failed verify byte ? verify byte ? fail fail yes yes no pass pass yes no erase program busy flag = 0 nop 5 10 no yes yes no
36 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version auto erase command when writing 30 16 twice continuously to the flash command regis- ter, the flash memory control circuit executes the auto erase se- quence described below for the area specified beforehand by the erase/program area select bits. (1) data 00 16 " is written to the area to be erased in the flash memory. (2) the erasure is executed. (3) the contents of the erased flash memory is erase-verified one by one. when the address which is not erased is found, verification is interrupted, and after the erase command is executed again, erase-verification is operated again. (4) when the erasure of all areas specified to be erased, is con- firmed by erase-verify-operation, the auto erase command is ended. the auto erase/erase/program busy flag of the flash memory control register becomes 1" when auto erase starts, and becomes 0" when auto erase completes. accordingly, cpu can recognize the comple- tion of auto erase by polling this bit. during auto erase, watchdog timer stops with ff 16 set. note: when the flash memory is erased by using the auto erase command, it is unnecessary to execute the erase and erase verify commands. figure 25 shows the flowchart when auto erase is executed. dc electric characteristics note: the characteristic of the flash memory part are the same as the standard of the parallel i/o mode. ac electric characteristics note: the characteristics are the same as the standards of the mi- crocomputer mode. reset command the reset command is a command to discontinue the program, erase, or the auto erase command on the way. when ff 16 is writ- ten to the command register two times continuously after 40 16 , 20 16 , or 30 16 is written to the flash command register, the pro- gram, erase, or auto erase command becomes invalid (reset), and the M37754FFCGP and the m37754ffchp enters the reset mode. the contents of the memory does not change even if the reset com- mand is executed. fig. 25 flowchart when program/erase/auto erase is executed (2) start write auto-erase command nop 5 10 30 16 device passed auto erase yes erase program busy flag = 0 write auto-erase command 30 16 no
37 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version absolute maximum ratings recommended operating conditions (vcc = 5 v10 %, ta = -20 to 85 c, unless otherwise noted) notes 1: average output current is the averaage value of a 100 ms interval. 2: the sum of i ol(peak) for ports p0, p1, p2, p3, p8, p10, and p11 must be 80 ma or less, the sum of i oh(peak) for ports p0, p1, p2, p3, p8, p10, and p11 must be 80 ma or less, the sum of i ol(peak) for ports p4, p5, p6, p7, and p9 must be 110 ma or less, the sum of i oh(peak) for ports p4, p5, p6, p7, and p9 must be 80 ma or less. 3: when the clock source select bit is 1, f(x in )s maximum limit is 12.5 mhz at low-speed running and is 20 mhz at high-speed running. symbol v cc av cc v i v i v o p d t opr t stg parameter power source voltage analog power source voltage input voltage reset, cnv ss , byte input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 5 , p10 0 Cp10 7 , p11 0 Cp11 7, v ref , x in output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 5 , p10 0 Cp10 7 , p11 0 Cp11 7 , x out , e power dissipation operating temperature storage temerature unit v v v ratings C0.3 to 7 C0.3 to 7 C0.3 to 12 (note) C0.3 to v cc +0.3 C0.3 to v cc +0.3 300 C20 to 85 C40 to 150 v v mw c c symbol v cc av cc v ss av ss v ih v ih v ih v il v il v il i oh(peak) i oh(peak) i oh(avg ) i oh(avg) i ol(peak) i ol(peak) i ol(avg) i ol(avg) f(x in ) parameter supply voltage analog supply voltage supply voltage analog supply voltage high-level input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 5 , x in , ______ reset, cnv ss , byte high-level input voltage p10 0 Cp10 7 , p11 0 Cp11 7 (in single-chip mode) high-level input voltage p10 0 Cp10 7 , p11 0 Cp11 7 (in memory expansion mode and microprocessor mode) low-level input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 5 , x in , ______ reset, cnv ss , byte low-level input voltage p10 0 Cp10 7 , p11 0 Cp11 7 (in single-chip mode) low-level input voltage p10 0 Cp10 7 , p11 0 Cp11 7 (in memory expansion mode and microprocessor mode) high-level peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 3 , p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 , p9 0 C p9 2 , p9 5 , p10 0 C p10 7 , p11 0 C p11 7 p9 3 , p9 4 high-level average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 3 , p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 0 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 , p9 0 C p9 2 , p9 5 , p10 0 C p10 7 , p11 0 C p11 7 p9 3 , p9 4 low-level peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 3 , p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 4 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 , p9 0 , p9 5 , p10 0 C p10 7 , p11 0 C p11 7 p5 0 Cp5 3 , p9 1 Cp9 4 low-speed running high-speed running limits min. 4.5 0.8 v cc 0.8 v cc 0.5 v cc 0 0 0 ty p . 5.0 v cc 0 0 max. 5.5 v cc v cc v cc 0.2 v cc 0.2 v cc 0.16 v cc C10 C20 C5 C15 10 20 5 15 25 40 unit v v v v v v v v v v ma ma ma ma ma ma ma ma mhz low-level average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 3 , p2 7 , p3 0 C p3 3 , p4 0 C p4 7 , p5 4 C p5 7 , p6 0 C p6 7 , p7 0 C p7 7 , p8 0 C p8 7 , p9 0 , p9 5 , p10 0 C p10 7 , p11 0 C p11 7 p5 0 Cp5 3 ,p9 1 Cp9 4 external clock frequency input (note 3) note: for the cnvss pin, this is 12.6 v when programming to the flash memory.
38 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version electrical characteristics (vcc = 5 v, vss = 0 v, ta = C20 to 85 c, f(x in ) = 40 mhz (note) ) symbol v oh v oh v oh v ol v ol parameter high-level output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p2 7 , p3 1 , p3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 2 , p9 5 , p10 0 Cp10 7 , p11 0 Cp11 7 high-level output voltage p0 0 Cp0 7, p1 0 Cp1 7 , p2 0 Cp2 3 , p2 7 , p3 1 , p3 3 , p9 0 Cp9 2 , p10 0 Cp10 7 , p11 0 Cp11 7 high-level output voltage _ e, p3 0 , p3 2 high-level output voltage p9 3 , p9 4 low-level output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p2 7 , p3 1 , p3 3 , p4 0 Cp4 7 , p5 4 Cp5 7 , p6 0 Cp6 7 ,p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 , p9 5 , p10 0 Cp10 7 , p11 0 Cp11 7 low-level output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p2 7 , p3 1 , p3 3 , p9 0 , p10 0 Cp10 7 , p11 0 Cp11 7 low-level output voltage _ e, p3 0 , p3 2 low-level output voltage p5 0 Cp5 3 , p9 1 Cp9 4 hysteresis _____ ____ hold, rdy, ta0 in Cta4 in , ____ ____ _____ tb0 in Ctb2 in , int 0 Cint 4 , ad trg , ____ ____ cts 0 , cts 1 , clk 0 , clk 1 , rxd 0 , rxd 1 hysteresis ______ _____ ____ reset, hold, rdy hysteresis x in high-level input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 5 , p10 0 Cp10 7 , p11 0 Cp11 7 , x in , reset, cnv ss , byte low-level input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 3 , p2 7 , p3 0 Cp3 3 , p4 0 Cp4 7 , p5 0 Cp5 3 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 0 Cp9 5 , p10 0 Cp10 7 , p11 0 Cp11 7 , x in , reset, cnv ss , byte low-level input current p5 4 C p5 7 , p9 5 ram hold voltage power supply current (target value) test conditions i oh = C10 ma i oh = C400 a min. limits 3.4 4.8 3.4 4.8 3.4 4.8 0.4 0.2 0.1 C0.25 2 ty p . C0.5 max. 2 unit v v v v v v v v v v v a a a ma v note: f(x in ) = 20 mhz when the clock source select bit = 1. v oh v ol v ol v t+ vt C v t+ vt C v t+ vt C i ih i il i oh = C10 ma i oh = C400 a i oh = C15 ma i oh = C600 a i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma i ol = 20 ma i ol = 2 ma 0.45 1.6 0.4 2 0.4 v i = 5 v 1 0.5 0.3 i il v ram v i = 0 v 5 C5 v i = 0 v, no pull-up transistor v i = 0 v, pull-up transistor used when clock is stoped. f(x in ) = 40 mhz, square waveform (note) ta = 25 c when clcock is stopped. ta = 85 c when clcock is stopped. output-only pin is open and other pins are vss during reset. a 25 ma C5 C1.0 50 1 20 i cc
39 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version a-d converter characteristics (v cc = av cc = 5 v 10 %, v ss = av ss = 0 v, t a = C20 to 85 c, the clock source select bit = 0, unless otherwise noted) unit parameter symbol test conditions limits ty p . min. max. a-d converter selected comparator selected 10-bit mode 8-bit mode comparator 8-bit mode comparator 10-bit mode 8-bit mode comparator 8-bit mode comparator 10-bit mode 8-bit mode comparator r ladder t conv v ref v ia resolution absolute accuracy ladder resistance conversion time reference voltage analog input voltage v ref = v cc v ref = v cc v ref = v cc high-speed running (f(x in ) 40 mhz) (note 2) low-speed running (f(x in ) 25 mhz) (note 2) 250 khz f ad 12.5 mhz 250 khz f ad 20 mhz (note 1) f ad = f(x in )/4 selected f ad = f(x in )/2 selected 5 5.9 4.9 1.4 2.45 0.7 4.72 3.92 1.12 2.7 0 10 v ref 3 2 40 3 60 20 v cc v ref 1 256 bits v lsb lsb mv lsb mv k w s v v notes 1 : this is valid when the high-speed running is selected. 2 : when the clock source select bit = 1, f(x in ) is 20 mhz or less at the high-speed running, and f(x in ) is 12.5 mhz or less at the low-speed running. d-a converter characteristics (v cc = 5 v, v ss = av ss = 0 v, v ref = 5 v, t a = C20 to 85 c, unless otherwise noted) unit parameter symbol limits typ. min. max. test conditions resolution absolute accuracy set time output resistance reference power supply input current t su r o i vref (note) 1 2.5 8 1.0 3 4 3.2 bits % s k w ma note: the test conditions are as follows: ? one d-a converter is used. ? the d-a register value of the unused d-a converter is 00 16 . ? the reference power supply input current of the ladder resistance of the a-d converter is excluded.
40 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version peripheral device input/output timing (v cc = 5 v10 %, v cc = 0 v, t a = C20 to 85 c, unless otherwise noted) * if the values depends on external clock frequency f(x in ), formulas of the limits are shown below. also, the values at f(x in ) = 40 mhz in high- speed running and at f(x in ) = 25 mhz in low-speed running are shown in ( ). at this time, the clock source select bit is 0. when the clock source select bit is 1, regard f(x in ) in tables as 2f(x in ). * the rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. timer a input (up-down input in event counter mode) t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in -up) symbol ta i out input cycle time ta i out input high-level pulse width ta i out input low-level pulse width ta i out input setup time ta i out input hold time parameter limits min. 2000 1000 1000 400 400 max. ns ns ns ns ns unit timer a input (external trigger input in pulse width modulation mode) t w(tah) t w(tal) symbol ta i in input high-level pulse width ta i in input low-level pulse width parameter min. 80 80 limits max. ns ns unit limits symbol parameter min. max. unit 8 10 9 f(x in ) 4 10 9 f(x in ) (200) (160) t c(ta) t w(tah) t w(tal) ta i in input cycle time ta i in input high-level pulse width ta i in input low-level pulse width ns ns ns ns 80 80 timer a input (external trigger input in one-shot pulse mode) limits symbol parameter min. max. unit 16 10 9 f(x in ) 8 10 9 f(x in ) 8 10 9 f(x in ) 4 10 9 f(x in ) 8 10 9 f(x in ) 4 10 9 f(x in ) (400) (320) (200) (160) (200) (160) f(x in ) 40 mhz (x in ) 25 mhz f(x in ) 40 mhz f(x in ) 25 mhz f(x in ) 40 mhz f(x in ) 25 mhz t c(ta) t w(tah) t w(tal) ta i in input cycle time ta i in input high-level pulse width ta i in input low-level pulse width ns ns ns ns ns ns timer a input (gating input in timer mode) note : the tai in input cycle time requires 4 or more cycles of count source. the tai in input high-level pulse width and the tai in input low-level pulse width respectively require 2 or more cycles of the count source. the limits in the table are the values when the count source is f(x in )/4 in high-speed running (f(x in ) 40 mhz) and when the count source is f(x in )/2 in low-speed running (f(x in ) 25 mhz). at this time, the clock source select bit is 0. timer a input (count input in event counter mode) t c(ta) t w(tah) t w(tal) symbol ta i in input cycle time ta i in input high-level pulse width ta i in input low-level pulse width parameter min. 80 40 40 limits max. ns ns ns unit f(x in ) 40 mhz f(x in ) 25 mhz
41 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version t c(ta) t su(ta jin -ta jout ) t su(ta jout -ta jin ) symbol parameter min. 800 200 200 limits max. ns ns ns unit timer a input (two-phase pulse input in event counter mode) ta i in input cycle time ta j in input setup time ta j out input setup time tai in input tai out input (up-down input) tai out input (up-down input) tai in input (when count by falling) tai in input (when count by rising) taj in input taj out input test conditions ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, vih = 4.0 v ?up-down and count input in event counter mode ?two-phase pulse input in event counter mode ?count input in event counter mode ?gating input in timer mode ?external trigger input in one-shot pulse mode ?external trigger input in pulse width modulation mode tc (ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in -up) t su(taj in -taj out ) t su(taj in -taj out ) t su(taj out -taj in ) t su(taj out -taj in ) t c(ta) t su(up-t in )
42 preliminar y notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos micr ocomputer flash memor y version t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) timer b input (count input in e v ent counter mode) symbol tbi in input cycle time (one edge count) tbi in input high-level pulse width (one edge count) tbi in input low-level pulse width (one edge count) tbi in input cycle time (both edge count) tbi in input high-level pulse width (both edge count) tbi in input low-level pulse width (both edge count) parameter limits min. 80 40 40 160 80 80 max. ns ns ns ns ns ns unit limits symbol parameter min. max. unit 16 10 9 f(x in ) 8 10 9 f(x in ) 8 10 9 f(x in ) 4 10 9 f(x in ) 8 10 9 f(x in ) 4 10 9 f(x in ) (400) (320) (200) (160) (200) (160) f(x in ) 40 mhz f(x in ) 25 mhz f(x in ) 40 mhz f(x in ) 25 mhz f(x in ) 40 mhz f(x in ) 25 mhz t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns ns ns ns timer b input (pulse per iod measurement mode) note : the tbi in input cycle time requires 4 or more cycles of count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of the count source. t he limits in the table are the values when the count source is f(x in )/4 in high-speed running (f(x in ) 40 mhz) and when the count source is f(x in )/2 in low-speed running (f(x in ) 25 mhz). at this time, the clock source select bit is 0. limits symbol parameter min. max. unit 16 10 9 f(x in ) 8 10 9 f(x in ) 8 10 9 f(x in ) 4 10 9 f(x in ) 8 10 9 f(x in ) 4 10 9 f(x in ) (400) (320) (200) (160) (200) (160) f(x in ) 40 mhz f(x in ) 25 mhz f(x in ) 40 mhz f(x in ) 25 mhz f(x in ) 40 mhz f(x in ) 25 mhz t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns ns ns ns timer b input (pulse width measurement mode) note : the tbi in input cycle time requires 4 or more cycles of count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of the count source. t he limits in the table are the values when the count source is f(x in )/4 in high-speed running (f(x in ) 40 mhz) and when the count source is f(x in )/2 in low-speed running (f(x in ) 25 mhz). at this time, the clock source select bit is 0. t c(ad) t w(adl) symbol ad trg input cycle time (minimum allowable trigger) ad trg input low-level pulse width parameter min. 1000 125 limits max. ns ns unit a-d trigger input
43 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version t c(ck) t w(ckh) t w(ckl) t d(c-q) t h(c-q) t su(d-c) t h(c-d) serial i/o symbol clk i input cycle time clk i input high-level pulse width clk i input low-level pulse width t x d i output delay time t x d i hold time r x d i input setup time r x d i input hold time parameter limits min. 200 100 100 0 20 90 max. 80 ns ns ns ns ns ns ns unit t w(inh) t w(inl) symbol int i input high-level pulse width int i input low-level pulse width parameter min. 250 250 limits max. ns ns unit external interrupt int i input t c(tb) t w(tbh) t w(tbl) t c(ck) t w(ckh) t w(ckl) t h(c - q) t d(c - q) t su(d - c) t w(inh) t w(inl) t h(c - d) t c(ad) t w(adl) tbi in input inti input ad trg input clki txdi rxdi test conditions ?vcc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v,v oh = 2.0 v,c l = 100 pf
44 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version ready, hold timing timing requirements (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 40 mhz when the clock source select bit = 0 * , unless otherwise noted) * the rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. t su(rdy- f 1) t su(hold- f 1) t h( f 1-rdy) t h( f 1-hold) symbol rdy input setup time hold input setup time rdy input hold time hold input hold time parameter limits min. 42 42 0 0 max. ns ns ns ns unit * : f(x in ) = 20 mhz when the clock source select bit = 1. switching characteristics (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 40 mhz when the clock source select bit = 0 * , unless otherwise noted) t d( f 1-hlda) t pxz(hlda-rdz) t pxz(hlda-wrz) t pxz(hlda-bhez) t pxz(hlda-az) t pxz(hlda-dlz/dhz) t pzx(hlda-rdz) t pzx(hlda-wrz) t pzx(hlda-bhez) t pzx(hlda-az) t pzx(hlda-dlz/dhz) symbol hlda output delay time floating start delay time (at hold state) floating start delay time (at hold state) floating start delay time (at hold state) floating start delay time (at hold state) floating start delay time (at hold state) floating release delay time (at hold state) floating release delay time (at hold state) floating release delay time (at hold state) floating release delay time (at hold state) floating release delay time (at hold state) parameter min. limits max. 50 50 50 50 50 50 ns ns ns ns ns ns ns ns ns ns ns unit 0 0 0 0 0 * : f(x in ) = 20 mhz when the clock source select bit = 1.
45 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version rdy input (when 3- f access in high-speed running) hold input test conditions ?v cc = 5 v10 % ? rdy input, hold input : v il = 1.0 v, v ih = 4.0 v ? hlda output : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf f 1 rd,wr rdy input t su(rdy- f 1) t h( f 1-rdy) ] rdy input is always sampled at the falling edge of f 1 just before the rd and wr signals?rise regardless of the bus mode and the number of waits. f 1 hold input hlda output rd wr bhe output a 0 ? 7 output a 8 ? 15 output a 16 ? 23 output d 0 ? 7 output d 8 ? 15 output (byte =?? t su(hold- f 1) t d( f 1-hlda) t pxz(hlda-rdz) t pxz(hlda-wrz) t pxz(hlda-bhe) t pxz(hlda-az) t pxz(hlda-dlz/dhz) t pzx(hlda-rdz) t pzx(hlda-wrz) t pzx(hlda-bhe) t pzx(hlda-az) t pzx(hlda-dlz/dhz) t d( f 1-hlda) t h( f 1-hold) hi-z hi-z hi-z hi-z hi-z
46 preliminar y notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos micr ocomputer flash memor y version timing requirements (v cc = 5 v10 %, v ss = 0 v , t a = e20 to 85 ?c , f(x in ) = 40 mhz when the cloc k source select bit = 0 ] , unless otherwise noted) ] the r ise and f all time of input signal m ust be 100 ns or less respectiv ely , unless otherwise noted. single-chip mode t c t w(h) t w(l) t r t f t su(pidee) t h(eepid) symbol external clock input cycle time (note 1) external clock input high-level pulse width (note 2) external clock input low-level pulse width (note 2) external clock rise time external clock fall time p or t pi input setup time (i = 0?11) p or t pi input hold time (i = 0?11) parameter min. 25 t c /2 e 8 t c /2 e 8 60 0 limits max. 8 8 ns ns ns ns ns ns ns unit t d(eepiq) symbol p or t pi data output dela y time (i = 0?11) parameter min. limits max. 60 ns unit switc hing characteristics (v cc = 5 v10 %, v ss = 0 v , t a = e20 to 85 ?c , f(x in ) = 40 mhz when the cloc k source select bit = 0 ] , unless otherwise noted) (single-chip mode) ] : f(x in ) = 20 mhz when the clock source select bit = 1 notes 1: when the cloc k source select bit = 1, t c ? s minim um limit is 50 ns . 2: when the clock source select bit = 1, set t w(h) /t c and t w(l) /t c ratios to 45 to 55 %. ] : f(x in ) = 20 mhz when the clock source select bit = 1 f(x in ) e port pi output (i = 0?11) port pi input (i = 0?11) t r t f t c t w(h) t w(l) t d(e e piq) t su(pid e e) t h(e e pid) test conditions v cc = 5 v 10 % intput timing voltage : v il = 1.0 v, v ih = 4.0 v output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf
47 preliminary notice: this is not a final specification. some parametric limits are subject to change. itsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version timing requirements (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 25 mhz when the clock source select bit = 0 * , unless otherwise noted) ] the rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. memory expansion and microprocessor mode : low-speed running ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit t c t w(h) t w(l) t r t f t su(dh-rd) t su(dl-rd) t su(pidCrd) t h(rd-dh) t h(rd-dl) t h(rdCpid) t su(aCdl/dh) t su(csCdl/dh) t su(laCdl) symbol external clock input cycle time (note 1) external clock input high-level pulse width (note 2) external clock input low-level pulse width (note 2) external clock rise time external clock fall time high-order data input setup time (byte = l) low-order data input setup time port pi input setup time (i = 49, 11) high-order data input hold time (byte = l) low-order data input hold time port pi input hold time (i = 49, 11) data setup time with address stabilized (note 3) data setup time with chip select stabilized (note 3) data setup time with address stabilized (note 3) parameter min. 40 t c /2 C 8 t c /2 C 8 30 30 60 0 0 0 limits max. 8 8 60 (2- f access) 140 (3- f access) 220 (4- f access) 60 (2- f access) 140 (3- f access) 220 (4- f access) 55 (2- f access) 135 (3- f access) 215 (4- f access) * : f(x in ) = 12.5 mhz when the clock source selet bit = 1 notes 1: when the clock source select bit = 1, t c s minimum limit is 80 ns. 2: when the clock source select bit = 1, set t w(h) /t c and t w(l) /t c ratios to 45 to 55 %. 3: since the values depend on external clock input frequency f(x in ), calculate them using the bus timing data formula on the page after the next page.
48 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version switching characteristics (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 25 mhz when the clock source select bit = 0 * , unless otherwise noted) memory expansion and microprocessor mode : low-speed running symbol parameter unit t w( f h) , t w( f l) t d( f 1Cwr) t d( f 1Crd) __ t w(wr) __ t w(rd) t d(aCwr) t d(aCrd) t d(aCale) t d(bheCwr) t d(bheCrd) t d(bheCale) t d(csCwr) t d(csCrd) t d(csCale) t d(wrCdlq/dhq) t pxz(wrCdlz/dhz) t d(aleCwr) t d(aleCrd) t w(ale) t h(wrCa) t h(rdCa) t h(wrCbhe) t h(rdCbhe) t h(wrCcs) t h(rdCcs) t h(wrCdlq/dhq) t pzx(wrCdlz/dhz) t d(laCwr) t d(laCrd) t d(laCale) t h(aleCla) t pxz(rdCdlz) t pzx(rdCdlz) t d(wrCpiq) f high-level pulse width, f low-level pulse width (note) ___ wr output delay time __ rd output delay time ___ wr low-level pulse width (note) rd low-level pulse width (note) address output delay time (note) address output delay time (note) address output delay time (note) ____ bhe output delay time (note) ____ bhe output delay time (note) ____ bhe output delay time (note) chip select output delay time (note) chip select output delay time (note) chip select output delay time (note) data output delay time floating start delay time (note) ale output delay time ale output delay time ale pulse width (note) address hold time (note) address hold time (note) bhe hold time (note) bhe hold time (note) chip select hold time (note) chip select hold time (note) data hold time (note) floating release delay time address output delay time (note) address output delay time (note) address output delay time (note) address hold time floating start delay time floating release delay time (note) port pi data output delay time (i = 49, 11) min. 20 C7 C7 60 60 15 15 8 15 15 8 15 15 8 4 4 22 10 10 10 10 10 10 15 0 12 12 5 9 18 2- f access max. 12 12 35 30 5 60 3- f access min. 20 C7 C7 140 140 15 15 8 15 15 8 15 15 8 4 4 22 10 10 10 10 10 10 15 0 12 12 5 9 18 max. 12 12 35 30 5 60 min. 20 C7 C7 140 140 95 95 55 95 95 55 95 95 55 4 4 62 10 10 10 10 10 10 15 0 92 92 52 25 (note) 18 4- f access max. 12 12 35 30 5 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns * : f(x in ) = 12.5 mhz when the clock source selet bit = 1 note: since the values depend on external clock input frequency f(x in ), calculate them using the bus timing data formula on the next page.
49 preliminary notice: this is not a final specification. some parametric limits are subject to change. itsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version 5 10 9 f(x in ) 5 10 9 f(x in ) 4 10 9 f(x in ) bus timing data formulas memory expansion and microprocessor mode : low-speed running (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) 25 mhz when the clock source select bit = 0 * , unless otherwise noted) t su(aCdl/dh) t su(csCdl/dh) t w( f h) , t w( f l) __ __ t w(wr) , t w(rd) t d(aCwr) t d(aCrd) t d(aCale) t d(bheCwr) t d(bheCrd) t d(bheCale) t d(csCwr) t d(csCrd) t d(csCale) t w(ale) t h(wrCa) t h(rdCa) t d(wrCbhe) t d(rdCbhe) t d(wrCcs) symbol data setup time with address stabilized data setup time with chip select stabilized f high-level pulse width, f low-level pulse width ___ ___ wr, rd low-level pulse width address output delay time address output delay time address output delay time ____ bhe output delay time ____ bhe outupt delay time ____ bhe output delay time chip select output delay time chip select output delay time chip select output delay time ale pulse width address hold time address hold time ____ bhe hold time ____ bhe hold time chip select hold time chip select holt time data hold time floating start delay time data setup time with address stabilized address output delay time address output delay time address output delay time address hold time floating release delay time parameter 3 10 9 f(x in ) 3 10 9 f(x in ) 1 10 9 f(x in ) 2 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 3 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 2- f access C 60 C 60 C 20 C 20 C 25 C 25 C 32 C 25 C 25 C 32 C 25 C 25 C 32 C 18 C 30 C 30 C 30 C 30 C 30 C 30 C 25 C 10 C 65 C 28 C 28 C 35 C 22 C 60 C 60 C 20 3- f access unit C 60 C 60 C 25 C 25 C 65 C 25 C 25 C 65 C 25 C 25 C 65 C 18 4- f access 7 10 9 f(x in ) 7 10 9 f(x in ) 3 10 9 f(x in ) 3 10 9 f(x in ) 3 10 9 f(x in ) 3 10 9 f(x in ) 3 10 9 f(x in ) 3 10 9 f(x in ) 3 10 9 f(x in ) 3 10 9 f(x in ) 3 10 9 f(x in ) 2 10 9 f(x in ) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t d(rdCcs) t h(wrCdlq/dhq) t pxz(wrCdlz/dhz) t su(laCdl) t d(laCwr) t d(laCrd) t d(laCale) t h(aleCla) t pzx(rdCdlz) C 65 5 10 9 f(x in ) 7 10 9 f(x in ) 3 10 9 f(x in ) 3 10 9 f(x in ) 2 10 9 f(x in ) 1 10 9 f(x in ) C 65 C 28 C 28 C 28 C 15 ] : f(x in ) 12.5 mhz when the clock source select bit = 1 note: when the clock source select bit is 1, regard f(x in ) in tables as 2f(x in ).
50 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version d 8 to d 15 output (byte = ?? f 1 f(x in ) ale output rd wr bhe output a 0 to a 7 output cs 0 to cs 4 output a 8 toa 15 output a 16 toa 23 output port pi output t w( f h) t w(h) t w(l) t r t f t c t w( f l) t d( f 1 -wr) t w(wr) t d( f 1 -wr) t w(ale) t d(bhe-wr) t d(bhe-ale) t d(a-ale) t d(cs-wr) t h(wr-cs) t d(cs-ale) hi-z t h(wr-dlq/dhq) t pxz(wr-dlz/dhz) t d(wr-piq) output data t d(a-wr) t h(wr-bhe) t h(wr-a) t d(ale-wr) address d 0 /la 0 to d 7 /la 7 output (multiplex bus (note) ) chip select note: these become a multiplex bus only when all of the following conditions are satisfied: ?byte = ? ?multiplex bus select bit = ? ?while the address which corresponds to chip select signal cs 4 is accessed test conditions (except port pi, f(x in )) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v t pzx(wr-dlz/dhz) t d(wr-dlq/dhq) d 0 to d 7 output test conditions (port pi, f(x in )) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf t d(wr-dlq) t h(ale-la) t h(wr-dlq) t d(la-wr) t d(la-ale) data address (when 2- f access in low-speed running )
51 preliminary notice: this is not a final specification. some parametric limits are subject to change. itsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version (when 2- f access in low-speed running ) f 1 f(x in ) ale output rd wr bhe output a 0 a 7 output cs 0 cs 4 output a 8 a 15 output a 16 a 23 output d 0 d 7 input d 8 d 15 input (byte = ?? t w( f h) t w(h) t w(l) t r t f t c t w( f l) t d( f 1 -rd) t d( f 1 -rd) t w(rd) t w(ale) t d(bhe-rd) t d(bhe-ale) t d(a-ale) t d(cs-rd) hi-z t h(rd-cs) t d(cs-ale) t su(dl/dh-rd) t h(rd-dl/dh) t su(pid-rd) t h(rd-pid) input data input data t d(a-rd) t h(rd-bhe) t h(rd-a) t d(ale-rd) address chip select t su(a-dl/dh) t su(cs-dl/dh) data t pzx(rd-dlz) t h(rd-dl) t pxz(rd-dlz) t d(la-ale) t su(dl-rd) t d(la-rd) t su(la-dl) t h(ale-la) la 0 la 7 output (d 0 /la 0 d 7 /la 7 ) (multiplex bus (note) ) d 0 d 7 input (multiplex bus (note) ) port pi input address note: these become a multiplex bus only when all of the following conditions are satisfied: ?byte = ? ?multiplex bus select bit = ? ?while the address which corresponds to chip select signal cs 4 is accessed test conditions (port pi, f(x in )) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v
52 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version (when 3- f access in low-speed running ) f 1 f(x in ) ale output rd wr bhe output a 0 a 7 output cs 0 cs 4 output a 8 a 15 output a 16 a 23 output d 0 d 7 output d 8 d 15 output (byte = ?? port pi output t w( f h) t w(h) t w(l) t r t f t c t w( f l) t d( f 1 -wr) t d( f 1 -wr) t w(wr) t w(ale) t d(bhe-wr) t d(bhe-ale) t d(a-ale) t h(wr-cs) t d(cs-wr) t d(cs-ale) t d(wr-dlq/dhq) t h(wr-dlq/dhq) t pxz(wr-dlz/dhz) t pzx(wr-dlz/dhz) t d(wr-piq) output data t d(a-wr) t h(wr-bhe) t h(wr-a) t d(ale-wr) address chip select note: these become a multiplex bus only when all of the following conditions are satisfied: ?yte = ? ?ultiplex bus select bit = ? ?hile the address which corresponds to chip select signal cs 4 is accessed test conditions (port pi, f(x in )) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v t h(ale-la) t d(wr-dlq) t d(la-ale) t d(la-wr) t h(wr-dlq) address data d 0 /la 0 d 7 /la 7 output (multiplex bus (note) )
53 preliminary notice: this is not a final specification. some parametric limits are subject to change. itsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version (when 3- f access in low-speed running ) f 1 f(x in ) ale output rd wr bhe output a 0 ? 7 output cs 0 ?s 4 output a 8 ? 15 output a 16 ? 23 output d 0 ? 7 input d 8 ? 15 input (byte = ?? port pi input t w( f h) t w(h) t w(l) t r t f t c t w( f l) t d( f 1 -rd) t d( f 1 -rd) t w(rd) t w(ale) t d(bhe-rd) t d(bhe-ale) t d(a-ale) t d(cs-rd) t h(rd-cs) t d(cs-ale) t su(dl/dh-rd) t h(rd-dl/dh) t su(pid-rd) t h(rd-pid) input data input data t d(a-rd) t h(rd-bhe) t h(rd-a) t d(ale-rd) address chip select t su(a-dl/dh) t su(cs-dl/dh) t su(a-dl/dh) t su(cs-dl/dh) note: these become a multiplex bus only when all of the following conditions are satisfied: ?byte = ? ?multiplex bus select bit = ? ?while the address which corresponds to chip select signal cs 4 is accessed test conditions (port pi, f(x in )) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v t pxz(rd-dlz) t h(ale-la) t h(rd-dl) t d(la-ale) t su(dl-rd) t d(la-rd) t pzx(rd-dlz) t su(la-dl) address la 0 ?a 7 output (d 0 /la 0 ? 7 /la 7 ) (multiplex bus (note) ) d 0 ? 7 input (multiplex bus (note) ) data
54 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version (when 4- f access in low-speed running ) f 1 f(x in ) ale output rd wr bhe output a 0 ? 7 output cs 0 ?s 4 output a 8 ? 15 output a 16 ? 23 output d 0 ? 7 output d 8 ? 15 output (byte = ?? port pi output t w( f h) t w(h) t w(l) t r t f t c t w( f l) t d( f 1 -wr) t d( f 1 -wr) t w(wr) t w(ale) t d(bhe-wr) t d(bhe-ale) t d(a-ale) t d(cs-wr) t h(wr-cs) t d(cs-ale) t d(wr-dlq/dhq) t h(wr-dlq/dhq) t pxz(wr-dlz/dhz) t pzx(wr-dlz/dhz) t d(rd-piq) t d(a-wr) t h(wr-bhe) t h(wr-a) t d(ale-wr) address chip select note: these become a multiplex bus only when all of the following conditions are satisfied: ?byte = ? ?multiplex bus select bit = ? ?while the address which corresponds to chip select signal cs 4 is accessed test conditions (port pi, f(x in )) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v output data t d(wr-dlq) t h(ale-la) t h(wr-dlq) t d(la-ale) t d(la-wr) address data d 0 /la 0 ? 7 /la 7 output (multiplex bus (note) )
55 preliminary notice: this is not a final specification. some parametric limits are subject to change. itsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version (when 4- f access in low-speed running ) f 1 f(x in ) ale output rd wr bhe output a 0 a 7 output cs 0 cs 4 output a 8 a 15 output a 16 a 23 output d 0 d 7 input d 8 d 15 input (byte =?? port pi input t w( f h) t w(h) t w(l) t r t f t c t w( f l) t d( f 1 -rd) t d( f 1 -rd) t w(rd) t w(ale) t d(bhe-rd) t d(bhe-ale) t d(a-ale) t d(cs-rd) t h(rd-cs) t d(cs-ale) t su(dl/dh-rd) t h(rd-dl/dh) t su(pid-rd) t h(rd-pid) input data input data t d(a-rd) t h(rd-bhe) t h(rd-a) t d(ale-rd) address chip select t su(cs-dl/dh) t su(a-dl/dh) note: these become a multiplex bus only when all of the following conditions are satisfied: ?byte = ? ?multiplex bus select bit = ? ?while the address which corresponds to chip select signal cs 4 is accessed test conditions (port pi, f(x in )) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v t pxz(rd-dlz) t h(ale-la) t su(dl-rd) t h(rd-dl) t pzx(rd-dlz) address t su(la-dl) data t d(la-rd) t d(la-ale) la 0 la 7 output (d 0 /la 0 d 7 /la 7 ) (multiplex bus ( note)) d 0 d 7 input (multiplex bus (note) )
56 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version min. 25 t c /2 C 8 t c /2 C 8 30 30 60 0 0 0 external clock input cycle time (note 1) external clock input high-level pulse width (note 2) external clock input low-level pulse width (note 2) external clock rise time external clock fall time high-order data input setup time (byte = l) low-order data input setup time port pi input setup time (i = 49, 11) high-order data input hold time (byte = l) low-order data input hold time port pi input hold time (i = 49, 11) data setup time with address stabilized (note 3) data setup time with chip select stabilized (note 3) data setup time with address stabilized (note 3) timing requirements (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in )=40 mhz when the clock source select bit = 0 * , unless otherwise noted) ] the rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted. memory expansion and microprocessor mode : high-speed running t c t w(h) t w(l) t r t f t su(dhCrd) t su(dlCrd) t su(pidCrd) t h(rdCdh) t h(rdCdl) t h(rdCpid) t su(aCdl/dh) t su(csCdl/dh) t su(laCdl) symbol parameter limits max. 8 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit 65 (3- f access) 110 (4- f access) 160 (5- f access) 65 (3- f access) 110 (4- f access) 160 (5- f access) 50 (3- f access) 100 (4- f access) 150 (5- f access) * : f(x in ) = 20 mhz when the clock source selet bit = 1 notes 1: when the clock source select bit = 1, t c s minimum limit is 50 ns. 2: when the clock source select bit = 1, set t w(h) /t c and t w(l) /t c ratios to 45 to 55 %. 3: since the values depend on external clock input frequency f(x in ), calculate them using the bus timing data formula on the page after the next page.
57 preliminary notice: this is not a final specification. some parametric limits are subject to change. itsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version switching characteristics (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) = 40 mhz when the clock source select bit = 0 * , unless otherwise noted) memory expansion and microprocessor mode : high-speed running symbol parameter unit t w( f h) , t w( f l) t d( f 1Cwr) t d( f 1Crd) __ t w(wr) __ t w(rd) t d(aCwr) t d(aCrd) t d(aCale) t d(bheCwr) t d(bheCrd) t d(bheCale) t d(csCwr) t d(csCrd) t d(csCale) t d(wrCdlq/dhq) t pxz(wrCdlz/dhz) t d(aleCwr) t d(aleCrd) t w(ale) t h(wrCa) t h(rdCa) t h(wrCbhe) t h(rdCbhe) t h(wrCcs) t h(rdCcs) t h(wrCdlq/dhq) t pzx(wrCdlz/dhz) t d(laCwr) t d(laCrd) t d(laCale) t h(aleCla) t pxz(rdCdlz) t pzx(rdCdlz) t d(wrCpiq) f high-level pulse width, f low-level pulse width ___ wr output delay time ___ rd output delay time ___ wr low-level pulse width ___ rd low-level pulse width address output delay time address output delay time address output delay time ____ bhe output delay time ____ bhe output delay time ____ bhe output delay time chip select output delay time chip select output delay time chip select output delay time data output delay time floating start delay time ale output delay time ale output delay time ale pulse width address hold time address hold time ____ bhe hold time ____ bhe hold time chip select hold time chip select hold time data hold time floating release delay time address output delay time address output delay time address output delay time address hold time floating start delay time floating release delay time port pi data output delay time (i = 49, 11) min. 5 C7 C7 55 55 25 25 10 25 25 10 25 25 10 4 4 10 10 10 10 10 10 10 15 0 15 15 5 10 15 3- f access max. 12 12 35 30 5 60 4 -f access min. 5 C7 C7 80 80 45 45 35 45 45 35 45 45 35 4 4 35 10 10 10 10 10 10 15 0 40 40 30 10 15 max. 12 12 35 30 5 60 min. 5 C7 C7 130 130 45 45 35 45 45 35 45 45 35 4 4 35 10 10 10 10 10 10 15 0 40 40 30 10 15 5- f access max. 12 12 35 30 5 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) (note) * : f(x in ) = 20 mhz when the clock source selet bit = 1 note: since the values depend on external clock frequency f(x in ), calculate them by using the bus timing data formulas on the next page.
58 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version 7 10 9 f(x in ) 7 10 9 f(x in ) 4 10 9 f(x in ) 3 10 9 f(x in ) 3 10 9 f(x in ) 2 10 9 f(x in ) 3 10 9 f(x in ) 3 10 9 f(x in ) 2 10 9 f(x in ) 3 10 9 f(x in ) 3 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 5 10 9 f(x in ) 5 10 9 f(x in ) 1 10 9 f(x in ) 3 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 1 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 1 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 5 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) t su(aCdl/dh) t su(csCdl/dh) t w( f h) , t w( f l) __ __ t w(wr) , t w(rd) t d(aCwr) t d(aCrd) t d(aCale) t d(bheCwr) t d(bheCrd) t d(bheCale) t d(csCwr) t d(csCrd) t d(csCale) t w(ale) t h(wrCa) t h(rdCa) t d(wrCbhe) t d(rdCbhe) t d(wrCcs) t d(rdCcs) t h(wrCdlq/dhq) t pxz(wrCdlz/dhz) t su(laCdl) t d(laCwr) t d(laCrd) t d(laCale) t d(aleCla) t pzx(rdCdlz) symbol data setup time with address stabilized data setup time with chip select stabilized f high-level pulse width, f low-level pulse width ___ ___ wr, rd low-level pulse width address output delay time address output delay time address output delay time ____ bhe outuput delay time ____ bhe outuput delay time ____ bhe outuput delay time chip select output delay time chip select output delay time chip select output delay time ale pulse width address hold time address hold time ____ bhe hold time ____ bhe hold time chip select hold time chip select hold time data hold time floating start delay time data setup time with address stabilized address outuput delay time address outuput delay time address outuput delay time address hold time floating release delay time parameter 3- f access 4- f access unit 5- f access ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns C 60 C 60 C 20 C 20 C 25 C 25 C 15 C 25 C 25 C 15 C 25 C 25 C 15 C 15 C 15 C 15 C 15 C 15 C 15 C 15 C 10 + 5 C 75 C 35 C 35 C 20 C 15 C 10 C 65 C 65 C 20 C 30 C 30 C 15 C 30 C 30 C 15 C 30 C 30 C 15 C 15 9 10 9 f(x in ) 9 10 9 f(x in ) 6 10 9 f(x in ) C 65 C 65 C 20 bus timing data formulas memory expansion and microprocessor mode : high-speed running (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) 40 mhz when the clock source select bit = 0 * , unless otherwise noted) 7 10 9 f(x in ) 3 10 9 f(x in ) 3 10 9 f(x in ) 2 10 9 f(x in ) C 75 C 35 C 35 C 20 ] : f(x in ) 20 mhz when the clock source select bit = 1 note: when the clock source select bit is 1, regard f(x in ) in tables as 2f(x in ). 9 10 9 f(x in ) C 75
59 preliminary notice: this is not a final specification. some parametric limits are subject to change. itsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version (when 3- f access in high-speed running ) f 1 f(x in ) ale output rd wr bhe output a 0 a 7 output cs 0 cs 4 output a 8 a 15 output a 16 a 23 output d 0 d 7 output d 8 d 15 output (byte = ?? port pi output t w( f h) t w(h) t w(l) t r t f t c t w( f l) t d( f 1 -wr) t d( f 1 -wr) t w(wr) t w(ale) t d(bhe-wr) t d(bhe-ale) t d(a-ale) t h(wr-cs) t d(cs-wr) t d(cs-ale) t h(wr-dlq/dhq) t pxz(wr-dlz/dhz) t d(wr-pjq) output data t d(a-wr) t h(wr-bhe) t h(wr-a) t d(ale-wr) address chip select t d(wr-dlq/dhq) t pzx(wr-dlz/dhz) note: these become a multiplex bus only when all of the following conditions are satisfied: ?byte = ? ?multiplex bus select bit = ? ?while the address which corresponds to chip select signal cs 4 is accessed test conditions (port pi, f(x in )) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v t d(wr-dlq) t h(ale-la) t h(wr-dlq) t d(la-ale) t d(la-wr) data address d 0 /la 0 d 7 /la 7 output (multiplex bus (note) )
60 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version (when 3- f access in high-speed running ) f 1 f(x in ) ale output rd wr bhe output a 0 a 7 output cs 0 cs 4 output a 8 a 15 output a 16 a 23 output d 0 d 7 input d 8 d 15 input (byte = ?? t w( f h) t w(h) t w(l) t r t f t c t w( f l) t d( f 1 -rd) t d( f 1 -rd) t w(rd) t w(ale) t d(bhe-rd) t d(bhe-ale) t d(a-ale) t d(cs-rd) t h(rd-cs) t d(cs-ale) t su(dl/dh-rd) t h(rd-dl/dh) t su(pid-rd) t h(rd-pid) input data input data t d(a-rd) t h(rd-bhe) t h(rd-a) t d(ale-rd) address chip select t su(cs-dl/dh) t su(a-dl/dh) t pxz (rd-dlz) t h(ale-la) t pzx(rd-dlz) t h(rd-dl) t su(dl-rd) t d(la-rd) t d(la-ale) t su (la-dl) address la 0 la 7 output (d 0 /la 0 d 7 /la 7 ) (multiplex bus (note) ) port pi input d 0 d 7 input (multiplex bus (note) ) data note: these become a multiplex bus only when all of the following conditions are satisfied: ?byte = ? ?multiplex bus select bit = ? ?while the address which corresponds to chip select signal cs 4 is accessed test conditions (port pi, f(x in )) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v
61 preliminary notice: this is not a final specification. some parametric limits are subject to change. itsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version (when 4- f access in high-speed running ) f 1 f(x in ) ale output rd wr bhe output a 0 a 7 output cs 0 cs 4 output a 8 a 15 output a 16 a 23 output d 0 d 7 output d 8 d 15 output (byte = ?? port pi output t w( f h) t w(h) t w(l) t r t f t c t w( f l) t d( f 1 -wr) t d( f 1 -wr) t w(wr) t w(ale) t d(bhe-wr) t d(bhe-ale) t d(a-ale) t h(wr-cs) t d(cs-wr) t d(cs-ale) t d(wr-dlq/dhq) t h(wr-dlq/dhq) t pxz(wr-dlz/dhz) t d(wr-piq) output data t d(a-wr) t h(wr-bhe) t h(wr-a) t d(ale-wr) address chip select t pzx(wr-dlz/dhz) note: these become a multiplex bus only when all of the following conditions are satisfied: ?byte = ? ?multiplex bus select bit = ? ?while the address which corresponds to chip select signal cs 4 is accessed test conditions (port pi, f(x in )) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v t d(la-wr) t d(la-ale) t h(wr-dlq) t d(wr-dlq) t h(ale-la) data address d 0 /la 0 d 7 /la 7 output (multiplex bus (note) )
62 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version (when 4- f access in high-speed running ) f 1 f(x in ) ale output rd wr bhe output a 0 a 7 output cs 0 ?s 4 output a 8 a 15 output a 16 a 23 output d 0 ? 7 input d 8 ? 15 input (byte = ?? t w ( f h) t w(h) t w(l) t r t f t c t w( f l) t d( f 1 -rd) t d( f 1 -rd) t w(rd) t w(ale) t d(bhe-rd) t d(bhe-ale) t h(rd-cs) t d(a-ale) t d(cs-rd) t d(cs-ale) t h(rd-dl/dh) t h(rd-pid) t su(pid-rd) t su(dl/dh-rd) input data input data t d(a-rd) t h(rd-bhe) t h(rd-a) t d(ale-rd) address chip select t su(cs-dl/dh) t su(a-dl/dh) la 0 ?a 7 output (d 0 /la 0 ? 7 /la 7 ) (multiplex bus (note) ) d 0 ? 7 input (multiplex bus (note) ) port pi input t su(dl-rd) t d(la-rd) t d(la-ale) t pxz(rd-dlz) address t su(la-dl) t pzx(rd-dlz) t h(rd-dl) t h(ale-la) data note: these become a multiplex bus only when all of the following conditions are satisfied: ?byte = ? ?multiplex bus select bit = ? ?while the address which corresponds to chip select signal cs 4 is accessed test conditions (port pi, f(x in )) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v
63 preliminary notice: this is not a final specification. some parametric limits are subject to change. itsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version (when 5- f access in high-speed running ) f 1 f(x in ) ale output rd wr bhe output a 0 a 7 output cs 0 cs 4 output a 8 a 15 output a 16 a 23 output d 0 d 7 output d 8 d 15 output (byte = ?? t w( f h) t w(h) t w(l) t r t f t c t w( f l) t d( f 1 -wr) t d( f 1 -wr) t w(wr) t w(ale) t d(bhe-wr) t d(bhe-ale) t d(a-ale) t h(wr-cs) t d(cs-wr) t d(cs-ale) t d(wr-dlq/dhq) t h(wr-dlq/dhq) t pxz(wr-dlz/dhz) t pzx(wr-dlz/dhz) t d(wr-piq) output data t d(a-wr) t h(wr-bhe) t h(wr-a) t d(ale-wr) address chip select note: these become a multiplex bus only when all of the following conditions are satisfied: ?byte = ? ?multiplex bus select bit = ? ?while the address which corresponds to chip select signal cs 4 is accessed test conditions (port pi, f(x in )) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v d 0 /la 0 d 7 /la 7 output (multiplex bus (note) ) port pi output t d(wr-dlq) t h(ale-la) t h(wr-dlq) data address t d(la-wr) t d(la-ale)
64 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version (when 5- f access in high-speed running ) f 1 f(x in ) ale output rd wr bhe output a 0 a 7 output cs 0 cs 4 output a 8 a 15 output a 16 a 23 output d 0 d 7 input d 8 d 15 input (byte = ?? t w( f h) t w(h) t w(l) t r t f t c t w( f l) t d( f 1 -rd) t d( f 1 -rd) t w(rd) t w(ale) t d(bhe-rd) t d(bhe-ale) t h(rd-cs) t d(a-ale) t d(cs-rd) t d(cs-ale) t h(rd-dl/dh) t h(rd-pid) t su(pid-rd) t su(dl/dh-rd) input data input data t d(a-rd) t h(rd-bhe) t h(rd-a) t d(ale-rd) address chip select t su(cs-dl/dh) t su(a-dl/dh) la 0 la 7 output (d 0 /la 0 d 7 /la 7 ) (multiplex bus (note) ) d 0 d 7 input (multiplex bus (note) ) port pi input t h(rd-dl) t su(dl-rd) t pxz(rd-dlz) t h(ale-la) t pzx(rd-dlz) data address t su(la-dl) t d(la-rd) t d(la-ale) note: these become a multiplex bus only when all of the following conditions are satisfied: ?yte = ? ?ultiplex bus select bit = ? ?hile the address which corresponds to chip select signal cs 4 is accessed test conditions (port pi, f(x in )) ?v cc = 5 v 10 % ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf test conditions (except port pi, f(x in )) ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf ?data input : v il = 0.8 v, v ih = 2.5 v
65 preliminary notice: this is not a final specification. some parametric limits are subject to change. itsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version f high-level pulse width, f low-level pulse width ___ wr output delay time ___ rd output delay time ___ wr low-level pulse width ___ rd low-level pulse width address output delay time address output delay time address output delay time ____ bhe output delay time ____ bhe output delay time ____ bhe output delay time chip select output delay time chip select output delay time chip select output delay time data output delay time floating start delay time ale output delay time ale output delay time ale pulse width address hold time address hold time ____ bhe hold time ____ bhe hold time chip select hold time chip select hold time data hold time floating release delay time t w( f h) , t w( f l) t d( f 1Cwr) t d( f 1Crd) __ t w(wr) __ t w(rd) t d(aCwr) t d(aCrd) t d(aCale) t d(bheCwr) t d(bheCrd) t d(bheCale) t d(csCwr) t d(csCrd) t d(csCale) t d(wrCdlq/dhq) t pxz(wrCdlz/dhz) t d(aleCwr) t d(aleCrd) t w(ale) t h(wrCa) t h(rdCa) t d(wrCbhe) t d(rdCbhe) t d(wrCcs) t d(rdCcs) t h(wrCdlq/dhq) t pzx(wrCdlz/dhz) symbol parameter unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns C 20 C 20 C 20 C 25 C 25 C 40 C 25 C 25 C 40 C 25 C 25 C 40 + 5 C 15 C 15 C 15 C 15 C 15 C 15 C 15 C 10 min. f (x in ) = 40 mhz ** 5 C7 C7 5 5 25 25 10 25 25 10 25 25 10 30 4 4 10 10 10 10 10 10 10 15 0 max. 12 12 35 bus timing data formula 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 2 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) 1 10 9 f(x in ) * : f(x in ) 20 mhz when the clock source select bit = 1. ** : f(x in ) = 20 mhz when the clock source select bit = 1. external bus timing when internal memory area is accessed (2- f access) in high-speed running (v cc = 5 v10 %, v ss = 0 v, t a = C20 to 85 c, f(x in ) 40 mhz when the clock source select bit = 0 * )
66 preliminary notice: this is not a final specification. some parametric limits are subject to change. mitsubishi microcomputers M37754FFCGP m37754ffchp shingle-chip 16-bit cmos microcomputer flash memory version f 1 f(x in ) ale output rd wr bhe output a 0 a 7 output cs 0 cs 4 output a 8 a 15 output a 16 a 23 output d 0 d 7 output d 8 d 15 output (byte = ?? ] the value of output data is undefined. t w( f h) t w(h) t w(l) t r t f t c t w(h) t w(l) t r t f t c t w( f l) t d( f 1 -wr) t d( f 1 -wr) t w(wr) t w(ale) t d(bhe-wr) t d(bhe-ale) t d(a-ale) t h(wr-cs) t d(cs-wr) t d(wr-dlq/dhq) t h(wr-dlq/dhq) t pxz(wr-dlz/dhz) t pzx(wr-dlz/dhz) hi-z t d(a-wr) t h(wr-bhe) t h(wr-a) t d(ale-wr) address t d(cs-ale) data t w( f h) t w( f l) t d( f 1 -rd) t d( f 1 -rd) t w(rd) t w(ale) t d(bhe-rd) t d(bhe-ale) t d(a-ale) t h(rd-cs) t d(cs-rd) hi-z t d(a-rd) t h(rd-bhe) t h(rd-a) t d(ale-rd) address t d(cs-ale) test conditions ?v cc = 5 v 10 % ?output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 100 pf (external bus timing on internal ram access (2- f access) in high-speed running)
? 1999 mitsubishi electric corp. new publication, effective apr. 1999. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our cu stomers in the selection of the mitsubishi semiconductor pro duct be st suited to the customer ? s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility fo r any damage, or infringement of any third-party ? s rights, originat ing in the use of any product data, diagrams, charts or circ uit application examples contained in these materials. all information contained in these materials, including prod uct data, diagrams and charts, represent information on prod ucts at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improveme nts or other reasons. it is therefore recommended that custo mers co ntact mitsubishi electric corporation or an authorized mitsu bishi semiconductor product distributor for the latest product information befor e purchasing a product listed herein. mitsubishi electric corporation semiconductors are not desig ned or manufactured for use in a device or system that is us ed unde r circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use o f a pro duct contained herein for any specific purposes, such as app aratus or systems for transportation, vehicular, medical, aerospace, nuclear, or u ndersea repeater use. the prior written approval of mitsubishi electric corporatio n is necessary to reprint or reproduce in whole or in part t hese ma terials. if these products or technologies are subject to the japanes e export control restrictions, they must be exported under a licens e from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control law s and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authori zed mitsubishi semiconductor product distributor for further detail s on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when m aking y our circuit designs, with appropriate measures such as (i) p lacement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mish ap.
rev. rev. no. date 1.0 first edition 971114 2.00 (1) for the timer a write flag (address 45 16 ), it?s name is corrected: 990428 new register name: timer a write register related pages: pages 11, 12 (2) for the following register, it?s internal status after reset is corrected: target register: processor mode register 0 (address 5e 16 ) correction: the status of bit 1 is 0. (not 1.) related page: page 12 revision description list M37754FFCGP, m37754ffchp data sheet (1/1) revision description

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